參數(shù)資料
型號(hào)： TMS320C31-80
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 18/132頁(yè)
文件大?。?/td> 1707K
代理商： TMS320C31-80
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SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options
(Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
EXTERNAL INTERRUPTS, CLOCK (CONTINUED)
CLKOUT
/IOPE0
73
51
51
1
Clock output or GPIO. This pin outputs either the CPU clock
(CLKOUT) or the watchdog clock (WDCLK). The selection
is made by the CLKSRC bit (bit 14) of the system control
and status register (SCSR). This pin can be used as a GPIO
if not used as a clock output pin.
(
↑
)
PDPINTB
137
95
95
Power drive protection interrupt input. This interrupt, when
activated, puts the PWM output pins (EVB) in the
high-impedance state should motor drive/power converter
abnormalities, such as overvoltage or overcurrent, etc.,
arise. PDPINTB is a falling-edge-sensitive interrupt.
(
↑
)
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS
XTAL1/CLKIN
123
87
87
24
PLL oscillator input pin. Crystal input to PLL/clock source
input to PLL. XTAL1/CLKIN is tied to one side of a reference
crystal.
XTAL2
124
88
88
25
Crystal output. PLL oscillator output pin. XTAL2 is tied to
one side of a reference crystal. This pin goes in the
high-impedance state when EMU1/OFF is active low.
PLLVCCA
IOPF6
12
10
10
39
PLL supply (3.3 V)
131
92
92
General-purpose I/O
(
↑
)
BOOT_EN /
XF
BOOT_EN
121
86
–
23
Boot ROM enable, GPO, XF. This pin will be sampled as
input (BOOT_EN) to update SCSR2.3 (BOOT_EN bit)
during reset and then driven as an output signal for XF. After
during reset and then driven as an out ut signal for XF. After
reset, XF is driven high. ROM devices do not have boot
ROM, hence, no BOOT_EN modes. The BOOT_EN pin
must be driven with a passive circuit only.
PLL loop filter input 1
XF
121
86
86
23
(
↑
)
PLLF
11
9
9
38
PLLF2
10
8
8
37
PLL loop filter input 2
VCCP (5V)
58
40
40
60
Flash programming voltage pin. This pin must be connected
to a 5-V supply for Flash programming. The Flash cannot
be programmed if this pin is connected to GND. When not
programming the Flash (i.e., during normal device
operation), this pin can either be left connected to the 5-V
supply or it can be tied to GND. This pin must not be left
floating at any time. Do not use any current-limiting resistor
in series with the 5-V supply on this pin. This pin is a
“
no
connect
”
(NC) on ROM parts and can be left open.
TP1
60
42
42
61
Test pin 1.
Do not connect.
TP2
Bold, italicized pin names
indicate pin function after reset.
GPIO
–
General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
–
Internal pullup
↓
–
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)
63
44
44
62
Test pin 2.
Do not connect.
相關(guān)PDF資料
PDF描述
TMS320C32-40 Digital Signal Processor
TMS320C32-50 Digital Signal Processor
TMS320C32-60 Digital Signal Processor
TMS320C32PGE40 32-Bit Digital Signal Processor
TMS320C32PGE50 32-Bit Digital Signal Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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