
SPRS145G
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JULY 2000
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REVISED FEBRUARY 2002
57
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
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1443
serial peripheral interface (SPI) module
Some 240xA devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted
into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications
between the DSP controller and external peripherals or another processor. Typical applications include external
I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice
communications are supported by the master/slave operation of the SPI.
The SPI module features include:
Four external pins:
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SPISOMI: SPI slave-output/master-input pin
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SPISIMO: SPI slave-input/master-output pin
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SPISTE: SPI slave transmit-enable pin
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SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
Two operational modes: master and slave
Baud rate: 125 different programmable rates/10 Mbps at 40-MHz CPUCLK
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
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Falling edge without phase delay: SPICLK active high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
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Falling edge with phase delay: SPICLK active high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
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Rising edge without phase delay: SPICLK inactive low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
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Rising edge with phase delay: SPICLK inactive low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE: All registers in this module are 16-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
register data is in the lower byte (7
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0), and the upper byte (15
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8) is read as zeros. Writing to the upper byte has no effect.