參數(shù)資料
型號(hào)： TMS320C28FNL
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁數(shù)： 127/132頁
文件大小： 1707K
代理商： TMS320C28FNL
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
127
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
peripheral register description (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
REG
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
KEY REGISTERS
077F0h
High Word of the 64 Bit KEY Register
High Word of the 64-Bit KEY Register
KEY3
077F1h
Third Word of the 64 Bit KEY Register
Third Word of the 64-Bit KEY Register
KEY2
077F2h
Second Word of the 64 Bit KEY Register
Second Word of the 64-Bit KEY Register
KEY1
077F3h
Low Word of the 64 Bit KEY Register
Low Word of the 64-Bit KEY Register
KEY0
PROGRAM MEMORY SPACE
–
FLASH REGISTERS
0xx00h
—
—
—
—
—
—
—
—
PMPC
—
—
—
—
PWR DWN
KEY1
KEY0
EXEC
0xx01h
—
—
—
—
—
—
WSVER EN
PRECND
Mode1
PRECND
Mode0
ENG/R
Mode2
ENG/R
Mode1
ENG/R
Mode0
FCM3
FCM2
FCM1
FCM0
CTRL
0xx02h
WADDR
0xx03h
WDATA
0xx04h
—
—
—
—
—
—
—
—
TCR
—
—
—
—
—
—
—
—
0xx05h
—
—
—
—
—
—
—
—
ENAB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0xx06h
—
—
—
—
SECT 4
ENABLE
SECT 3
ENABLE
SECT 2
ENABLE
SECT 1
ENABLE
SECT
I/O MEMORY SPACE
0FF0Fh
—
—
—
—
—
—
—
—
FCMR
—
—
—
—
—
—
—
—
WAIT-STATE GENERATOR CONTROL REGISTER
0FFFFh
—
—
—
—
—
BVIS.1
BVIS.0
ISWS.2
WSGR
ISWS.1
ISWS.0
DSWS.2
DSWS.1
DSWS.0
PSWS.2
PSWS.1
PSWS.0
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
Register shown with bits set in
register mode
.
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