參數(shù)資料
型號： TMS320C25FNA50
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 59/132頁
文件大?。?/td> 1707K
代理商： TMS320C25FNA50
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
59
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
SPI slave mode operation in LF2403A
The LF2403A device does not have the SPISTE/IOPC5 pin. (This function is available as an internal signal only.)
The following must be done to put the LF2403A SPI in slave mode:
1.
Configure SPISTE/IOPC5 signal for GPIO mode by clearing the MCRB.5 bit.
2.
Configure SPISTE/IOPC5 signal as an output (by writing a 1 to bit 13 of PCDATDIR) and drive it low (by
writing a 0 to bit 5 of PCDATDIR). Note that SPISTE/IOPC5 should not be driven low until after the SPI is
configured and taken out of reset.
NOTE: The slave SPISTE/IOPC5 signal must not be driven low until after the master
and
slave SPI modules
are configured and taken out of reset. The initialization sequence is as follows:
a.
The master SPI is configured first and taken out of reset. This ensures that the master SPICLK is
initialized to its appropriate level (high or low, depending on the polarity bit) first, before the slave SPI
starts accepting clock pulses.
b.
The slave SPI is configured and taken out of reset.
c.
The GPIO/SPI pins of the slave is then configured for SPI operation and the SPISTE/IOPC5 signal is
driven low. This is done
after
ensuring the correct level of the master SPICLK signal. One method of
doing this would be to read the level of the SPICLK pin through the PCDATDIR register and then
deciding on the appropriate course of action.
d.
SPI transmission may commence now. Transmission of data should not be attempted until both master
and slave are configured and the slave SPISTE/IOPC5 signal is driven low.
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