參數(shù)資料
型號： TMS320C206PZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 75/123頁
文件大小： 1205K
代理商： TMS320C206PZ
www.ti.com
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1
to enable 32-bit operations on the registers (along with 16-bit operations).
Table 4-15
shows the GPIO
register mapping.
Table 4-15. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
0x6F80
2
0x6F82
2
0x6F84
2
0x6F86
2
0x6F88
2
0x6F8A
2
0x6F8C
2
0x6F8E
2
0x6F8F
0x6F90
2
0x6F92
2
0x6F94
2
0x6F96
2
0x6F98
2
0x6F9A
2
0x6F9C
2
0x6F9E
2
0x6F9F
0x6FA0
32
0x6FBF
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
0x6FC0
2
0x6FC2
2
0x6FC4
2
0x6FC6
2
0x6FC8
2
0x6FCA
2
0x6FCC
2
0x6FCE
2
0x6FD0
16
0x6FDF
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
0x6FE0
1
GPIOXINT2SEL
0x6FE1
1
GPIOXNMISEL
0x6FE2
1
0x6FE3
reserved
5
0x6FE7
GPIOLPMSEL
0x6FE8
2
0x6FEA
reserved
22
0x6FFF
GPACTRL
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
GPAPUD
GPIO A Control Register (GPIO0 to 31)
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
GPIO A MUX 2 Register (GPIO16 to 31)
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pull Up Disable Register (GPIO0 to 31)
reserved
GPBCTRL
GPBQSEL1
GPBQSEL2
GPBMUX1
GPBMUX2
GPBDIR
GPBPUD
GPIO B Control Register (GPIO32 to 35)
GPIO B Qualifier Select 1 Register (GPIO32 to 35)
reserved
GPIO B MUX 1 Register (GPIO32 to 35)
reserved
GPIO B Direction Register (GPIO32 to 35)
GPIO B Pull Up Disable Register (GPIO32 to 35)
reserved
reserved
reserved
GPADAT
GPASET
GPACLEAR
GPATOGGLE
GPBDAT
GPBSET
GPBCLEAR
GPBTOGGLE
GPIO Data Register (GPIO0 to 31)
GPIO Data Set Register (GPIO0 to 31)
GPIO Data Clear Register (GPIO0 to 31)
GPIO Data Toggle Register (GPIO0 to 31)
GPIO Data Register (GPIO32 to 35)
GPIO Data Set Register (GPIO32 to 35)
GPIO Data Clear Register (GPIO32 to 35)
GPIO Data Toggle Register (GPIO32 to 35)
reserved
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XNMI GPIO Input Select Register (GPIO0 to 31)
LPM GPIO Select Register (GPIO0 to 31)
Peripherals
75
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