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TMS320AV410, TMS320AV411
DIGITAL NTSC/PAL ENCODER
SCSS020B – JULY 1996 – REVISED MAY 1997
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
video bus interface
Figure 6 and Figure 7 show video bus connections. Figure 6 shows connections to the TMS320AV220. Figure 7
shows connections to a general MPEG-2 video decoder. Because the connections shown in Figure 7 use two
’AV410 devices, composite, YC, and RGB signals can be obtained simultaneously.
video attribute insertion
The ’AV410/411 has capability to insert video information into the vertical blanking period. For example, the
’AV410/411 can insert a video attribute which indicates the proper aspect ratio to the video receiver. For NTSC
mode, the ’AV410/411 can insert 14-bit video information on line 20 of every field to conform to the EIAJ
CPX-1024 Video Aspect Ratio ID specification. Attribute information should be set using the ATR1 and ATR0
registers. The ATR2 register (bits 5:0) should be set with the 6-bit CRC data that is calculated by the following
equation:
G(X)
X
6
X
1
where
X
6
, X are preset to 1
Bit 7 of the ATR2 register enables attribute insertion.
For PAL mode, the ’AV410/411 can insert 14-bit video information on line 20 of every frame to conform to the
ETS 300-294 Wide Screen Signaling specification. Attribute information should be set in the ATR1 register and
bits 5:0 of the ATR2 register. Bit 7 of the ATR2 register enables attribute insertion.
In NTSC and PAL encoding modes, data in the ATR1 and ATR0 registers are transferred to internal circuitry
when the ATR2 register is set. For this reason, the ATR2 register should be set last.
TMS320AV220
CLK1OUT
HSYNC
VSYNC
D23–D0
VCLK
HSYNC
VSYNC
PD23–PD0
13.5 MHz
TMS320AV410/411
Composite
Y
C
Figure 6. Interface to TMS320AV220
MPEG-2
Video Decoder
CLK0
HSYNC
EVEN
VSYNC
D7–D0
PIXCLK
HSYNC
FIELD
D7–D0
27 MHz
TMS320AV410/411
Composite
Y
C
EXTEN
L
IMOD1, 0 = 0,0 OMOD = 0
CLK0
HSYNC
TMS320AV410/411
VSYNC
D7–D0
R
G
B
EXTEN
H
IMOD1, 0 = 0,0 OMOD = 1
Figure 7. Interface to MPEG-2 Video Decoder
P