參數(shù)資料
型號: TMS320AV120
英文描述: Digital Audio Decoder & Support
中文描述: 數(shù)字音頻解碼器
文件頁數(shù): 83/132頁
文件大?。?/td> 1707K
代理商: TMS320AV120
SPRS145G
JULY 2000
REVISED FEBRUARY 2002
83
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
RS timings
timing requirements for a reset [H = 0.5t
c(CO)
] (see Figure 26 and Figure 27)
MIN
NOM
MAX
UNIT
tw(RSL)
Pulse duration, stable CLKIN to RS high
8tc(CI)
cycles
tw(RSL2)
tp
td(EX)
Pulse duration, RS low
8tc(CI)
cycles
PLL lock-up time
4096tc(CI)
cycles
Delay time, reset vector executed after PLL lock time
36H
ns
XTAL1
Address/
Data/
Control
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
tOSCST is the oscillator start-up time, which is dependent on crystal/resonator and board design.
CLKOUT
RS
tw(RSL)
tp
td(EX)
VDD/VDDO
CLKIN
BOOT_EN
/XF
tOSCST
BOOT_EN
I/Os
XF
Code-Dependent
Address/Data/Control Valid
Hi-Z
Figure 26. Power-on Reset
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