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TMS320AV110
MPEG AUDIO DECODER
SCSS013C – MAY 1993 – REVISED AUGUST 1995
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register-access read cycle timing
Register-access read is initiated when the host sets R/W high and sets up the address of the register that is to
be read (see Figure 4). A setup time (t
su4
) later, the host asserts DCS. The ’AV110 uses the falling edge of DCS
to store the state of R/W and SADDR. The ’AV110 register-access controller drives WAIT low. The WAIT line
being low prevents the host from deasserting DCS. The ’AV110 completes the read cycle by taking WAIT high
and driving SDATA[7:0] with valid data. The host detects WAIT high and takes DCS high to latch the valid data
on SDATA[7:0]. When the ’AV110 releases WAIT, another read or write cycle can occur.
DCS
R/W
SADDR
(6:0)
Data to Decoder
Data From
Decoder
Write Cycle
Read Cycle
SDATA
(7:0)
WAIT
tsu4
th3
th3
tsu4
th4
th4
tsu5
tsu5
th5
tdis1
tdis2
tdis2
I
O
I
tsu7
ten2
ten2
tsu7
td1
ten1
tw2
tw3
tw2
tw3
tC2
tC1
tsu6
tpd2
tpd2
tsu1
REQ
tpd1
Input buffer is full
Data can be input
This REQ signal only applies when writing data to the DATAIN register.
Figure 4. Register-Access Read and Write Cycle Timing
register-access write cycle timing
The host can initiate a register access request while the ’AV110 is still busy with the prior request because an
access cycle requires from 166 ns to 250 ns w; the minimum DCS period is only 100 ns. The ’AV110 stores the
state of R/W and SADDR on the falling edge of DCS and drives WAIT low if it has not completed the prior request.
The WAIT output is used to prevent the host from deasserting DCS (see Figure 4). When the prior write request
is completed, the ’AV110 drives WAIT high. The host detects the WAIT high output and takes DCS high. The
’AV110 then releases WAIT and stores the data on the SDATA lines.