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參數(shù)資料
| 型號(hào)： | TMS28F512A-12C3DDE |
| 英文描述： | x8 Flash EEPROM |
| 中文描述： | x8閃存EEPROM的 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 311K |
| 代理商： | TMS28F512A-12C3DDE |
TMS28F512A
65536 BY 8-BIT
FLASH MEMORY
SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operation
Modes of operation are defined in Table 1.
Table 1. Operation Modes
FUNCTION
MODE
VPP
(1)
E
(22)
G
(24)
A0
(12)
A9
(26)
W
(31)
DQ0–DQ7
(13–15, 17–21)
Read
VPPL
VPPL
VPPL
VIL
VIL
VIH
VIL
VIH
X
X
X
VIH
VIH
X
Data Out
Output Disable
X
X
Hi-Z
Read
Standby and Write Inhibit
X
X
Hi-Z
Algorithm Selection Mode
Algorithm-Selection Mode
VPPL
VIL
VIL
VIL
VIH
X
VID
VIH
Mfr Equivalent Code 89h
Device Equivalent Code B8h
Read
VPPH
VPPH
VPPH
VPPH
VIL
VIL
VIH
VIL
VIL
VIH
X
VIH
X
VIH
VIH
X
Data Out
Read /
Write
Output Disable
X
X
Hi-Z
Standby and Write Inhibit
Write
X can be VIL or VIH.
VPPL
≤
VCC + 2 V; VPPH is the programming voltage specified for the device. For more details, see recommended operating conditions.
read/output disable
X
X
X
X
Hi-Z
Data In
VIL
When the outputs of two or more TMS28F512As are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of other devices. To
read the output of the TMS28F512A, a low-level signal is applied to the E and G pins. All other devices in the
circuit should have their outputs disabled by applying a high-level signal to one of these pins.
standby and write inhibit
Active I
CC
current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100
μ
A by applying
a high CMOS level on E. In this mode, all outputs are in the high-impedance state. The TMS28F512A draws
active current when it is deselected during programming, erasure, or program/erase verification. It continues
to draw active current until the operation is terminated.
algorithm-selection mode
The algorithm-selection mode provides access to a binary code that identifies the correct programming and
erase algorithms. This mode is activated when A9 is forced to V
ID
. Two identifier bytes are accessed by toggling
A0. All other addresses must be held low. A0 low selects the manufacturer equivalent code 89h, and A0 high
selects the device equivalent code B8h, as shown in Table 2.
Table 2. Algorithm-Selection Modes
IDENTIFIER
§
PINS
A0
VIL
VIH
DQ7
1
DQ6
0
DQ5
0
DQ4
0
DQ3
1
DQ2
0
DQ1
0
DQ0
1
HEX
89
Manufacturer Equivalent Code
Device Equivalent Code
§E = G = VIL, A1 – A8 = VIL, A9 = VID, A10–A15 = VIL, VPP = VPPL.
programming and erasure
1
0
1
1
1
0
0
0
B8
In the erased state, all bits are at a logic one. Before erasing the device, all memory bits must be programmed
to a logic zero. Afterwards, the entire chip is erased. At this point, the bits, now logic ones, can be programmed
accordingly. Refer to the fastwrite- and fasterase-algorithms for further detail.
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