
TMS28F512A
65536 BY 8-BIT
FLASH MEMORY
SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
functional block diagram
Erase-Voltage Switch
VPP
A0–A15
A
d
d
r
e
s
s
L
a
t
c
h
Column Decoder
Row Decoder
Chip-Enable and
Output-Enable
Logic
DQ0–DQ7
Program-Voltage
Switch
W
524 288-Bit
Array Matrix
To Array
STB
STB
Input/Output Buffers
E
G
State Control
Program/Erase
Stop Timer
Command Register
Data Latch
8
16
Column Gating