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| 型號： | TMS27C010A-15 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Programmable Read-Only Memory(128K×8結構,可擦可編程只讀存儲器) |
| 中文描述： | 可編程只讀存儲器（128K的× 8結構，可擦可編程只讀存儲器） |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 269K |
| 代理商： | TMS27C010A-15 |
TMS27C010A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS110B – NOVEMBER 1990 – REVISED JUNE 1995
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
IOH = – 20
μ
A
IOH = –2.5 mA
IOL = 2.1 mA
IOL = 20
μ
A
VI = 0 V to 5.5 V
VO = 0 V to VCC
VPP = VCC = 5.5 V
VPP = 13 V
VCC = 5.5 V,
VCC = 5.5 V,
MIN
MAX
UNIT
VOH
High-level dc output voltage
VCC–0.2
3.5
V
VOL
Low-level dc output voltage
0.4
V
0.1
±
1
±
1
10
II
IO
IPP1
IPP2
Input current (leakage)
μ
A
μ
A
μ
A
mA
Output current (leakage)
VPP supply current
VPP supply current (during program pulse)
50
ICC1
VCCsupply current (standby)
VCC supply current (standby)
TTL-input level
E = VIH
E = VCC
±
0.2 V
500
μ
A
CMOS-input level
100
ICC2
VCC supply current (active) (output open)
pp y
VCC = 5.5 V,
tcycle = minimum cycle time,
outputs open
E = VIL
30
mA
Minimum cycle time = maximum access time.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
PARAMETER
TEST CONDITIONS
VI = 0 V, f = 1 MHz
VO = 0 V, f = 1 MHz
MIN
TYP§
MAX
UNIT
pF
CI
CO
Capacitance measurements are made on sample basis only.
§All typical values are at TA = 25
°
C and nominal voltages.
Input capacitance
4
8
Output capacitance
6
10
pF
switching characteristics over recommended ranges of operating conditions (see Notes 4 and 5)
PARAMETER
TEST
CONDITIONS
’27C010A-10
’27C010A-12
’27PC010A-12
’27C010A-15
’27PC010A-15
’27C010A-20
’27PC010A-20
UNIT
MIN
MAX
100
MIN
MAX
120
MIN
MAX
150
MIN
MAX
200
ta(A)
ta(E)
ten(G)
Access time from address
CL = 100 pF,
1 Series 74
TTL load,
Input tr
≤
20 ns,
r
Input tf
≤
20 ns
100 F
ns
Access time from chip enable
100
120
150
200
ns
Output enable time from G
55
55
75
75
ns
tdis
Output disable time from G or
E, whichever occurs first
0
50
0
50
0
60
0
60
ns
tv(A)
Output data valid time after
change of address, E, or G,
whichever occurs first
Value calculated from 0.5-V delta to measured output level.
NOTES:
4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (reference AC testing waveform).
5. Common test conditions apply for tdis except during programming.
0
0
0
0
ns
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