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| 型號(hào)： | TMP93CF77 |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | TMP93CF77 |
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TMP93CF76/CF77/CW76/CU76/CT76
93CF76-4
2001-09-07
Figure 1.1 TMP93CF76/CF77/CW76/CU76/CT76 block diagram
Real Time
Counter
(RTC)
8-BIT PWM
(1CH)
14-BIT PWM
(3CH)
SIO
I
2
C bus I/F
(IIC)
DVCC
DGND
to SIO
VS
RMTU, RMTD
EXT
CFGTM
CTL, CFG, DFG, DPG
PCTL
HS
INT2, 3, 4
Others INT
X1
X2
PB0/XT1
PB1/XT2
TEST
CLK
CPU INT
P54/INT0
P53/INT1
ADREF
P40 to 47/AIN2 to 9
ADGND
P86/CSYNCIN
P82/RMTIN
P83/EXT/TO1
P84/DPGIN
P85/CFGIN
P81/DFGIN
P80/CTLIN
TEST1
TEST2
TEST3 (NC)
for P75 (AIN0)
P76 (AIN1)
to AD
P50/INT4/TI3 (TI5)/SI
P51/INT3/TI2 (TI4)
P52/INT2/TI1(TI0)
P73/SDA0
P74/SCL0
P75/AIN0/SDA1
P76/AIN1/SCL1
PWM0
PWM1
PA3/PWM2
P93/TPG03
P97/TPG11
P94/CR
P94/HA
P87/COMPIN
P51/SO
P52/SCK
PD0 to 1/G8 to 9
Vkk
(VFT Driver)
P20 to 27
P10 to17
P00 to 07
for
P50 (SI)
P96/TO1/TPG10
PC0 to 7/G0 to 7
PC0 to 5/S8 to 13
PE0 to 7/S0 to 7
to PWM3
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
SR
900/L CPU
W
A
B
D
H
L
IX
IY
IZ
SP
32 bit
F
P C
Port D
Port C
Port F
Port E
8-Bit Timer
(TC0)
16-Bit Timer
(TC1)
16-Bit Timer
(TC2)
16-Bit Timer
(TC3)
16-Bit Timer
(TC4)
16-Bit Timer
(TC5)
Timing Pulse
Generater
(TPG)
P91/TPG01/
VASWP
P90/TP0/TPG00
P92/TP1
Head Amp SW
Color Rotary
Interrupt
Controller
High frequency
OSC
(16 MHz)
Low frequency
OSC
(32 kHz)
Port 2
Port 1
Port 0
RAM
(2.0/2.5/4.0 KB)
ROM
(72/96/128/
166/192 KB)
Watchdog Timer
(WDT)
Time Base Timer
(TBC)
Capture
(Capture0, 1, 2)
8 BIT AD
Converter
(10 CH)
V-Separation
C-sync
RMT-Input
External-Input
Capture Input
(CAPIN)
VISS/VASS
CTL Duty
Detector
PV/PH
PA0/PWM3/
PVPH
for 8-BIT PWM
RESET
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相關(guān)代理商/技術(shù)參數(shù) |
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