- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382649 > TMP320F2810PGFS (Texas Instruments, Inc.) DIGITAL SIGNAL PROCESSORS PDF資料下載
參數(shù)資料
| 型號： | TMP320F2810PGFS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 60/103頁 |
| 文件大小： | 1341K |
| 代理商： | TMP320F2810PGFS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁當前第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
60
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
32-bit CPU-Timers 0/1/2 (continued)
Table 49. TIMERxTPR Register Bit Definitions
BITS
NAME
R/W
RESET
DESCRIPTION
7:0
TDDR
R/W
0x00
Timer Divide-Down. Every (TDDRH:TDDR + 1) timer clock source cycles, the timer counter
register (TIMH:TIM) decrements by one. At reset, the TDDRH:TDDR bits are cleared to 0. To
increase the overall timer count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC) value is 0, one timer clock source
cycle later, the contents of the TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC whenever the timer reload bit
(TRB) is set by software.
15:8
PSC
R
0x00
Timer Prescale Counter. These bits hold the current prescale count for the timer. For every timer
clock source cycle that the PSCH:PSC value is greater than 0, the PSCH:PSC decrements by one.
One timer clock (output of the timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and the timer counter register
(TIMH:TIM) decrements by one. The PSCH:PSC is also reloaded whenever the timer reload bit
(TRB) is set by software. The PSCH:PSC can be checked by reading the register, but it cannot be
set directly. It must get its value from the timer divide-down register (TDDRH:TDDR). At reset, the
PSCH:PSC is set to 0.
x = 0, 1, or 2
Table 50. TIMERxTPRH Register Bit Definitions
BIT
NAME
R/W
RESET
DESCRIPTION
7:0
TDDRH
R/W
0x00
See description of TIMERxTPR.
15:8
PSCH
R
0x00
See description of TIMERxTPR.
x = 0, 1, or 2
P
相關PDF資料 |
PDF描述 |
|---|---|
| TMX320TCI6482 | Communications Infrastructure Digital Signal Processor |
| TMX320TCI6482ZTZ | Communications Infrastructure Digital Signal Processor |
| TMX320TCI6482ZTZ8 | Communications Infrastructure Digital Signal Processor |
| TMX320TCI6482ZTZA | Communications Infrastructure Digital Signal Processor |
| TMX320TCI6482ZTZA8 | Communications Infrastructure Digital Signal Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMP320F2811GHHA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors |
| TMP320F2811GHHQ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors |
| TMP320F2811GHHS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors |
| TMP320F2811PBKA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors |
| TMP320F2811PBKQ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors |
發(fā)布緊急采購，3分鐘左右您將得到回復。