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    參數(shù)資料
    型號: TMP320F2810GHHMEP
    廠商: Texas Instruments, Inc.
    元件分類: 數(shù)字信號處理
    英文描述: Digital Signal Processors
    中文描述: 數(shù)字信號處理器
    文件頁數(shù): 53/103頁
    文件大?。?/td> 1341K
    代理商: TMP320F2810GHHMEP
    TMS320F2810, TMS320F2812
    DIGITAL SIGNAL PROCESSORS
    SPRS174B
    APRIL 2001
    REVISED SEPTEMBER 2001
    53
    POST OFFICE BOX 1443
    HOUSTON, TEXAS 77251
    1443
    watchdog block (continued)
    When the XRS line is low, the WDFLAG bit is forced low. The WDFLAG bit will only be set if a rising edge on
    WDRST signal is detected (after synch and a 4 cycle delay) and the XRS signal is high. If the XRS signal is low
    when WDRST goes high, then the WDFLAG bit will remain at 0. In a typical application, the WDRST signal will
    connect to the XRS input. Hence to distinguish between a watchdog reset and an external device reset, an
    external reset must be longer in duration then the watchdog pulse.
    Emulation Considerations
    The watchdog module behaves as follows under various debug conditions:
    CPU Suspended:
    When the CPU is suspended, the watchdog clock (WDCLK) is
    suspended.
    When the CPU is placed in run-free mode, then the watchdog module
    resumes operation as normal.
    When the CPU is in real-time single-step mode, the watchdog clock
    (WDCLK) is suspended. The watchdog remains suspended even within
    real-time interrupts.
    When the CPU is in real-time run-free mode, the watchdog operates as
    normal.
    Run-Free Mode:
    Real-Time Single-Step Mode:
    Real-Time Run-Free Mode:
    P
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