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參數(shù)資料
| 型號： | TMP122AMDBVTEP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO6 |
| 封裝： | GREEN, PLASTIC, SOT-23, 6 PIN |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 651K |
| 代理商： | TMP122AMDBVTEP |
DELAY TIME
TIMING DIAGRAMS
www.ti.com .......................................................................................................................................................................................... SBOS454 – NOVEMBER 2008
The Delay Bits control the amount of time delay between each conversion. This feature allows the user to
maximize power savings by eliminating unnecessary conversions, and minimizing current consumption. During
active conversion the TMP122 typically requires 50
A of current for approximately 0.25s conversion time, and
approximately 20
A for idle times between conversions. Delay settings are identified in Table 12 as conversion
time and period, and are shown in Figure 9. Default power up is D1/D0 equal 0/0. Conversion time and
conversion periods scale with resolution. Conversion period denotes time between conversion starts.
Table 12. Conversion Delay for 12-Bit Resolution
D1
D2
CONVERSION TIME
CONVERSION PERIOD
0
0.25 s
0
1
0.25 s
0.5 s
1
0
0.25 s
1 s
1
0.25 s
8 s
Figure 9. Conversion Time and Period Description
The TMP122 is SPI compatible. Figure 10 to Figure 12 describe the various timing parameters of the TMP122
with timing definitions in Table 13.
Table 13. Timing Description
PARAMETER
MIN
MAX
UNIT
t1
SCK period
100
ns
t2
Data in to rising edge SCK setup time
20
ns
t3
SCK falling edge to output data delay
30
ns
t4
SCK rising edge to input data hold time
20
ns
t5
CS to rising edge SCK set-up time
40
ns
t6
CS to output data delay
30
ns
t7
CS rising edge to output high impedance
30
ns
Copyright 2008, Texas Instruments Incorporated
11
Product Folder Link(s): TMP122-EP
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