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參數(shù)資料
| 型號： | TMC93LC86 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM |
| 中文描述： | 1K/2K/2K/4K/16K-Bit微型導(dǎo)線串行EEPROM |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 2006K |
| 代理商： | TMC93LC86 |
T
MC
93
L
C46/56/57/66/86
1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM
FEATURES
I
High speed operation:
– 93
L
C46/56/57/66
: 1MHz
– 93
L
C86
: 3MHz
I
Low power CMOS technology
I
1.8 to 6.0 volt operation
I
Selectable x8 or x16 memory organization
I
Self-timed write cycle with auto-clear
I
Hardware and software write protection
I
Power-up inadvertant write protection
I
1,000,000 Program/erase cycles
I
100 year data retention
I
Commercial, industrial and automotive
temperature ranges
I
Sequential read (except T
MC
93
L
C46)
I
Program enable (PE) pin (T
MC
93
L
C86 only)
93
L
C46/56/57/66/86 F02
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J,W)
CMOS EEPROM floating gate technology. The devices
are designed to endure 1,000,000 program/erase cycles
and have a data retention of 100 years. The devices are
available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP
packages.
DESCRIPTION
T
he
93
L
C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit
Serial EEPROM memory devices which are configured
as either registers of 16 bits (ORG pin at V
CC
) or 8 bits
(ORG pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The 93
L
C46/56/
57/66/86 are manufactured using
TMC
’s advanced
SOIC Package (S,V)
PIN FUNCTIONS
Pin Name
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
V
CC
+1.8 to 6.0V Power Supply
GND
Ground
ORG
Memory Organization
NC
No Connection
PE*
Program Enable
BLOCK DIAGRAM
Note: When the ORG pin is connected to VCC, the x16 organiza-
tion is selected. When it is connected to ground, the x8 pin
is selected. If the ORG pin is left unconnected, then an
internal pullup device will select the x16 organization.
SOIC Package (K,X)
2002 by
TMC
TSSOP Package (U,Y)**
8
7
6
5
VCC
NC (PE*)
ORG
GND
DI
DO
CS
SK
1
2
3
4
VCC
ADDRESS
DECODER
MEMORY ARRAY
ORGANIZATION
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
SK
CS
PE*
DI
ORG
GND
Doc. No. 1023, Rev. G
CS
SK
DI
DO
VCC
NC (PE*)
ORG
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
NC (PE*)
ORG
GND
1
2
3
4
8
7
6
5
VCC
CS
SK
ORG
GND
DO
DI
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
NC (PE*)
ORG
GND
1
2
3
4
8
7
6
5
NC (PE*)
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