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  • 參數(shù)資料
    型號: TMC22091R0C
    廠商: FAIRCHILD SEMICONDUCTOR CORP
    元件分類: 顏色信號轉(zhuǎn)換
    英文描述: Digital Video Encoders/Layering Engine
    中文描述: COLOR SIGNAL ENCODER, PQCC84
    封裝: PLASTIC, LCC-84
    文件頁數(shù): 37/60頁
    文件大小: 293K
    代理商: TMC22091R0C
    PRODUCT SPECIFICATION
    TMC22091/TMC22191
    37
    Master Mode
    In Master mode, initial timing is determined from the
    RESET input, and subsequent cycles result from pro-
    grammed values in the Timing Control Registers. The Hori-
    zontal Sync output, VHSYNC, goes LOW 18 PXCK clock
    cycles after the device is reset. The 50% point of the falling
    edge of sync LOW on line 4 of field 1 (NTSC) or line 1 of
    field 1 (PAL) occurs at the COMPOSITE and LUMA out-
    puts 56 clocks after reset, or 38 clocks after VHSYNC. See
    Figure 14, Master Mode Timing.
    Slave Mode
    In Slave mode, the 50% point of the falling edge of sync
    occurs 46 PXCK clocks after the falling edge of VHSYNC,
    which is an input signal to the TMC22x91. This must be pro-
    vided by the host to begin every line. If it is early, the line
    will be started early, maintaining the 52 clock delay to out-
    put. If it comes late, the front porch portion of the output
    waveform will be extended as necessary. See Figure 15,
    Slave Mode Timing.
    Figure 13. Slave Mode PD Port Interface Timing (Genlock Mode)
    Figure 14. Master Mode Timing
    tPWHPX
    tSP
    PXCK
    PCK
    LDV
    PD
    KEY
    VHSYNC
    (GHSYNC)
    tSP
    tHP
    tXL
    24340A
    tPWHLDV
    tPWLLDV
    2N+1
    2N+2
    2N+3
    tPWLVH
    tPWLPX
    PXCK
    0
    50% Sync Amplitude
    24353A
    1
    2
    3
    4
    16
    17
    18
    19
    20
    21
    51
    52
    53
    54
    55
    56
    57
    58
    59
    60
    RESET
    COMPOSITE
    OUTPUT
    VHSYNC
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