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參數(shù)資料
| 型號： | TMC22071AR1C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Phono Plug; Leaded Process Compatible:Yes; Gender:Male; Number of Contacts:3 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 125K |
| 代理商： | TMC22071AR1C |
TMC22071A
PRODUCT SPECIFICATION
8
Figure 4. Control Register Map
Control Register Bit Functions
Bit
0
Name
SRESET
Function
Software reset. When LOW, resets and holds internal state machines, resets Control
Register with previously written values, and disables output drivers. When HIGH,
SRESET starts and runs state machines, PXCK, and enables outputs.
Input signal format select.
Bit 3 is the MSB.
000 NTSC at 12.27 Mpps.
001 NTSC at 13.5 Mpps.
010 Reserved.
011 Reserved.
100 PAL at 13.5 Mpps.
101 Reserved.
11x Reserved.
Factory test control bits. These should be set LOW.
Video source select. Bit 8 is the MSB.
00 V
IN1
01 V
IN2
1x V
IN3
Video gain. When LOW, gain is set to unity. When HIGH, gain is set to 1.5X.
Factory test control bits. These should be set LOW.
These control bits allows the HSYNC, VSYNC, and sample clock to be time-shifted by
-16/32 to +15/32 pixels. Bit 16 is the two’s complement MSB. When SUBPIX is 00
h
,
HSYNC and incoming video are subject to LEADLAG. A value of 18
h
delays HSYNC
1/4 pixel. A value of 08
h
advances HSYNC 1/4 pixel.
This control word allows the HSYNC and VSYNC to be time-shifted -122 to +132 LDV
cycles. When LEADLAG is 7B
h
, HSYNC and incoming video are in alignment. A value of
83
h
delays HSYNC eight LDV cycles. A value of 73
h
advances HSYNC eight LDV
cycles. Bit 24 is the MSB.
1-3
FORMAT
4-6
7,8
TEST
SOURCE
9
10-11
12-16
VGAIN
TEST
SUBPIX
17-24
LEADLAG
0
0
0
0
0
0
0 0 0
0 0
0 0
1
0
0
0
S
L
A
F
V
T
B
D
C
F
T
T
T
C
L
T
T
(
(
B
T
T
G
S
T
S
(
L
S
V
7
8
15 16
23
24
31 32
39 40
46
47
54
STATUS REGISTER
65-22071-06
55
58
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