參數(shù)資料
型號(hào): TMC2072KHC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 消費(fèi)家電
英文描述: Genlocking Video Digitizer
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: MQFP-100
文件頁數(shù): 1/21頁
文件大?。?/td> 160K
代理商: TMC2072KHC
www.fairchildsemi.com
REV. 1.0.4 6/19/01
Features
Fully integrated acquisition
3-channel video input multiplexer
Two-stage (analog and digital) video clamp
Automatic gain adjustment
Sync detection and separation
Pixel and subpixel adjustment of video-to-sync output
timing
Genlock to any NTSC or PAL format, including PAL-M
and PAL-N
Pixel clock generation
8-bit video A/D conversion
Standard R-bus serial microprocessor interface
User-selectable line-locked pixel rates include:
– 12.27 MHz NTSC & PAL-M
– 13.5 MHz
NTSC & all PAL
– 14.75 MHz PAL (non-M) TMC2072-1 only
– 15.0 MHz
PAL (non-M) TMC2072-1 only
Direct interface to Fairchild Semiconductor video
encoders and decoders
Built-in circuitry for crystal oscillator
No tuning or external voltage reference required
Space-saving 100-lead MQFP package
Applications
Frame grabber
Digital videotape recorders
Desktop video
Description
The TMC2072 Genlocking Video Digitizer samples and
quantizes standard analog baseband composite NTSC
or PAL video into its 8-bit digital equivalent. It extracts
horizontal and vertical sync signals, from which an on-chip
PLL generates a line-locked pixel clock for the on-chip 8-bit
A/D converter and a double-speed register clock to transfer
data to a subsequent video processing subsystem. A second
PLL generates a chroma subcarrier locked to the incoming
chroma burst. The chip reports each line’s color burst phase
and frequency during the next horizontal sync pulse.
The TMC2072 includes a three-channel video input multi-
plexer, analog clamp, variable gain amplifier, and digital
back porch clamp. The user may provide either an external
20MHz clock or a 20MHz crystal. No external component
changes or tuning are required for PAL or NTSC operation at
either D1 or square pixel VGA pixel rates.
The TMC2072 is fabricated in a submicron CMOS process
and is packaged in a 100-lead MQFP. Its performance is
guaranteed from 0 to 70°C.
Block Diagram
VIN1
ANALOG
CLAMP
GAIN
D/A
GVSYNC
GHSYNC
PXCK
LDV
VALID
65-2072-01
CVBS7-0
BACK PORCH
CLAMP
DATA
SELECTOR
SUBCARRIER
PHASE-LOCKED
LOOP
SYNC
SEPARATOR
HORIZONTAL
PHASE-LOCKED
LOOP
DIRECT
DIGITAL
SYNTHESIZER
LOWPASS
FILTER
D/A
+1.2V
R
S
S
S
I
C
C
C
O
D
O
P
P
E
C
V
R
R
CONTROL
MICROPROCESSOR
INTERFACE
ANALOG INTERFACE
DDS/PIXEL CLOCK INTERFACE
M
VIN2
VIN3
A/D
TMC2072
Genlocking Video Digitizer
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