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參數(shù)資料
| 型號： | TM2SN64EPU-12A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 存儲器模塊 |
| 英文描述： | SYNCHRONOUS DYNAMIC RAM MODULES |
| 中文描述： | 同步動態(tài)RAM模塊 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 271K |
| 代理商： | TM2SN64EPU-12A |
TM2SN64EPU 2097152 BY 64-BIT
TM4SN64EPU 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAMMODULES
SMMS681 – AUGUST 1997
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
serial presence detect (continued)
Table 2. Serial Presence-Detect Data for the TM4SN64EPU
BYTE
NO.
DESCRIPTION OF FUNCTION
TM4SN64EPU-12A
TM4SN64EPU-12
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written into serial memory during
module manufacturing
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD memory device
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM, EDO, SDRAM, . . .)
SDRAM
04h
SDRAM
04h
3
Number of row addresses on this assembly
11
0Bh
11
0Bh
4
Number of column addresses on this assembly
9
09h
9
09h
5
Number of module banks on this assembly
2 banks
02h
2 banks
02h
6
Data width of this assembly
64 bits
40h
64 bits
40h
7
Data width continuation
00h
00h
8
Voltage interface standard of this assembly
LVTTL
01h
LVTTL
01h
9
SDRAM cycle time at maximum supported CAS latency
(CL), CL = X
tCK = 12 ns
C0h
tCK = 12 ns
C0h
10
SDRAM access from clock at CL = X
tAC = 9 ns
90h
tAC = 9 ns
90h
11
DIMM configuration type (non-parity, parity, error correcting
code [ECC])
Non-Parity
00h
Non-Parity
00h
12
Refresh rate/type
15.6
μ
s/
self-refresh
80h
15.6
μ
s/
self-refresh
80h
13
SDRAM width, primary DRAM
x8
08h
x8
08h
14
Error-checking SDRAM data width
N/A
00h
N/A
00h
15
Minimum clock delay, back-to-back random column
addresses
1 CK cycle
01h
1 CK cycle
01h
16
Burst lengths supported
1, 2, 4, 8
0Fh
1, 2, 4, 8
0Fh
17
Number of banks on each SDRAM device
2 banks
02h
2 banks
02h
18
CAS latencies supported
2, 3
06h
2, 3
06h
19
CS latency
0
01h
0
01h
20
Write latency
0
01h
0
01h
21
SDRAM module attributes
Non-buffered/
Non-registered
00h
Non-buffered/
Non-registered
00h
22
SDRAM device attributes: general
VDD tolerance =
(+10%)/(–5%).
Burst read/write,
precharge all,
auto precharge
1Eh
VDD tolerance =
(+10%),
Burst read/write,
precharge all,
auto precharge
0Eh
23
Minimum clock cycle time at CL = X – 1
tCK = 15 ns
tAC = 9 ns
N/A
F0h
tCK = 18 ns
tAC = 10 ns
N/A
30h
24
Maximum data-access time from clock at CL = X – 1
90h
A0h
25
Minimum clock cycle time at CL = X – 2
00h
00h
26
Maximum data-access time from clock at CL = X – 2
N/A
00h
N/A
00h
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