TLV99028
3V, 10BIT, 28MSPS AREA CCD ANALOG FRONT END
SLAS300A AUGUST 2000 REVISED MARCH 2004
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
ground and decoupling
All ground pins of the TLV990-28 are not internally connected and must be connected externally to PCB ground.
General practices should apply to the PCB design to limit high-frequency transients and noise that are fed back
into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.
In the case of power supply decoupling, 0.1-
F ceramic chip capacitors are adequate to keep the impedance
low over a wide frequency range. Recommended external decoupling for the three voltage-reference pins is
shown in Figure 4. Since their effectiveness depends largely on the proximity to the individual supply pin, all
decoupling capacitors should be placed as close as possible to the supply pins.
To reduce high-frequency and noise coupling, it is highly recommended that digital and analog grounds be
shorted immediately outside the package. This can be accomplished by running a low-impedance line between
DGND and AGND under the package.
automatic optical black and offset correction
In the TLV990-28, the optical black and system channel-offset corrections are performed by an autodigital
feedback loop. Two DACs are used to compensate for both channel offset and optical black offset. A coarse
correction DAC (CDAC) is located before the PGA gain stage, and a fine correction DAC (FDAC) is located after
the gain stage. The digital-calibration system is capable of correcting the optical black and channel offset down
to one ADC LSB accuracy.
The TLV990-28 automatically starts autocalibration whenever the OBCLP input is pulled low. The OBCLP pulse
should be wide enough to cover one positive half cycle of the ADCCLK, as shown in Figure 1.
For each line, the optical black pixels plus the channel offset are sampled and converted to digital data by the
ADC. A digital circuit averages the data during the optical black pixels. The averaged result is compared digitally
with the desired output code stored in the Vb register (default is 40H), then control logic adjusts the FDAC to
make the ADC output equal to the Vb. If the offset is out of the range of the FDAC (
±255 ADC LSBs), the error
is corrected by both CDAC and FDAC. The CDAC increments or decrements by one CDAC LSB, depending
on whether the offset is negative of positive, until the output is within the range of the FDAC. The remaining
residue is corrected by the FDAC.
The relationship among the FDAC, CDAC, and ADC in terms of number of ADC LSBs is as follows:
1 FDAC LSB = 1 ADC LSB,
1 CDAC LSB = PGA linear gain
× n ADC LSB.
Where n is:
4 for 0 =< gain code <128
3 for 128 =< gain code <192
2 for 192 =< gain code <256
1 for 256 =< gain code
For example, if PGA gain = 2 (6 dB), then, 1 CDAC LSB = 2 x 3 ADC LSBs = 6 ADC LSBs.
After autocalibration is complete, the ADC’s digital output during CCD signal interval can be expressed by the
following equation:
ADC output [D9D0] = CCD_input
× PGA gain + Vb,
Where Vb is the desired black level selected by the user. The total offset, including optical black offset, is
calibrated to be equal to Vb by adjusting the offset correction DACs during autocalibration.