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參數(shù)資料
| 型號： | TLV571IPWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | GREEN, PLASTIC, TSSOP-24 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 479K |
| 代理商： | TLV571IPWG4 |
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TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
Table 1. Conversion Modes
START OF
CONVERSION
OPERATION
COMMENTS – FOR INPUT
Hardware start
(CSTART)
CR0.D5 = 0
Repeated conversions from AIN
CSTART falling edge to start sampling
CSTART rising edge to start conversion
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
CSTART rising edge must be applied
a minimum of 5 ns before or after CLK
rising edge.
Software start
CR0.D5 = 1
Repeated conversions from AIN
WR rising edge to start sampling initially. Thereafter, sampling occurs at the
rising edge of RD.
Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT
mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
With external clock, WR and RD rising
edge must be a minimum 5 ns before
or after CLK rising edge.
configure the device
The device can be configured by writing to control registers CR0 and CR1.
Table 2. TLV571 Programming Examples
REGISTER
INDEX
D5
D4
D3
D2
D1
D0
COMMENT
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
COMMENT
EXAMPLE1
CR0
0
Normal, INT OSC
CR1
0
1
0
Binary
EXAMPLE2
CR0
0
1
0
Power down, EXT OSC
CR1
0
1
0
1
0
2’s complement output
power down
The TLV571 offers two power down modes, auto power down and software power down. This device will
automatically proceed to auto power down mode if RD is not present one clock after conversion. Software power
down is controlled directly by the user by pulling CS to DVDD.
Table 3. Power Down Modes
PARAMETERS/MODES
AUTO POWER DOWN
SOFTWARE POWER DOWN
(CS = DVDD)
Maximum power down dissipation current
1 mA
10
A
Comparator
Power down
Clock buffer
Power down
Control registers
Saved
Minimum power down time
1 CLK
2 CLK
Minimum resume time
1 CLK
2 CLK
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