參數(shù)資料
型號(hào): TLV5633C
廠商: Texas Instruments, Inc.
英文描述: 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
中文描述: 2.7 V至5.5 V低功耗12位數(shù)字到模擬,具有內(nèi)部參考和斷電變換器
文件頁(yè)數(shù): 15/22頁(yè)
文件大?。?/td> 301K
代理商: TLV5633C
TLV5633C, TLV5633I
2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
SLAS190 – MARCH 1999
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
The offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full scale code and the lowest code that produces a positive output voltage.
TLV5633 interfaced to an Intel MCS
51 controller
The circuit in Figure 15 shows how to interface the TLV5633 to an Intel MCS
51 microcontroller. The address
bus and the data bus of the controller are multiplexed on port 0 (non page mode) to save port pins. To separate
the address bits and the data bits, the controller provides a dedicated signal, address latch enable (ALE), which
is connected to a latch at port 0.
An address decoder is required to generate the chip select signal for the TLV5633. In this example, a simple
3-to-8 decoder (74AC138) is used for the interface as shown in Figure 15. The DAC is memory mapped at
addresses 0x8000/1/2/3 within the data memory address space and mirrored every 32 address locations
(0x8020/1/2/3, 0x8040/1/2/3, etc.). In a typical microcontroller system, programmable logic should be used to
generate the chip select signals for the entire system.
The data pins and the WE pin of the TLV5633 can be connected directly to the multiplexed address and data
bus and the WR signal of the controller.
The application uses the TLV5633 device’s internal reference at 2.048 V. The LDAC pin is connected to P3.5
and is used to update the DAC after both data bytes have been written.
P2 A(15–8)
P0 AD(7–0)
ALE
WR
D(7–0)
A
B
C
G1
G2A
G2B
A(1–0)
D(7–0)
CS
WE
REF
A(15–0)
AD(7–0)
CS(7–0)
DVDD
DVDD
8
8
8
16
8
8
RL
74AC373
8xC51
74AC138
TLV5633
A15
A2
A3
A4
2
Q(7–0)
Y(7–0)
G2A
SPD
PWR
LDAC
LE
OE
OUT
To Other Devices Requiring
Voltage Reference
P3.5
Figure 15. TLV5633 Interfaced to an Intel MCS
51 Controller
MCS is a registered trademark of Intel Corporation.
相關(guān)PDF資料
PDF描述
TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
TLV5636D 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
TLV5636DGK 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
TLV5637D 2.7 V TO 5.5 V LOW POWER DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
tlv5639(中文) 2.7V to 5.5V Low Power 12-Bit Digital-to-Analog Converters with Internal Reference and Power Down(2.7V-5.5V,12位低功耗,帶自動(dòng)掉電和內(nèi)部基準(zhǔn)的DAC)
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