參數(shù)資料
型號: TLV5618
廠商: Texas Instruments, Inc.
英文描述: 2.7-V to 5.5-V Low-Power Dual 12-Bit Digital-to-Analog Converter with Power Down(2.7-5.5V低功耗雙12位,帶掉電D/A轉(zhuǎn)換器)
中文描述: 2.7 V至5.5 V低功耗雙12位數(shù)字到模擬轉(zhuǎn)換器斷電(2.7 - 5.5V的低功耗雙12位,帶掉電的D / A轉(zhuǎn)換器)
文件頁數(shù): 4/18頁
文件大?。?/td> 275K
代理商: TLV5618
TLV5618A
2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT
DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS230G
JULY 1999
REVISED AUGUST 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 4.5 V to
VDD 4.5 V to
5 5 V
5.5 V
Fast
1.8
2.5
mA
C & I
suffixes
Slow
Fast
0 8
0.8
1.6
1
IDD
Power supply current
No load, All inputs = AGND or
No load, All in uts = AGND or
VDDDAC latch = All ones
VDD, DAC latch = All ones
VDD = 2.7 V to
VDD 2.7 V to
3 3 V
3.3 V
2.2
mA
Slow
0 6
0.6
0 9
0.9
Fast
1 8
1.8
2 3
2.3
VDD = 2.7 V to
VDD 2.7 V to
5.5 V
M & Q
suffixes
mA
Slow
0.8
1
Power down supply current
1
μ
A
PSRR
Power supply rejection ratio
Zero scale, See Note 2
65
dB
Full scale, See Note 3
65
NOTES:
2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax)
EZS(VDDmin)/VDDmax]
3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax)
EG(VDDmin)/VDDmax]
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
12
bits
INL
Integral nonlinearity
See Note 4
±
2
±
4
±
1
LSB
DNL
Differential nonlinearity
See Note 5
±
0.5
LSB
EZS
Zero-scale error (offset error at zero
scale)
See Note 6
±
12
mV
EZS (TC)
Zero-scale-error temperature
coefficient
See Note 7
3
ppm/
°
C
C & I suffixes
VDD = 4.5 V
5.5 V
VDD = 2.7 V
3.3 V
VDD = 2.7 V
5.5 V
±
0.29
±
0.6
±
0.6
% f ll
% full
scale V
EG
Gain error
See Note 8
M & Q suffixes
EG (TC)
NOTES:
Gain-error temperature coefficient
See Note 9
1
ppm/
°
C
4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale, excluding the effects of zero-code and full-scale errors.
5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal
1-LSB amplitude change of any two adjacent codes.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax)
EZS (Tmin)]/2Vref
×
106/(Tmax
Tmin).
8. Gain error is the deviation from the ideal output (2Vref
1 LSB) with an output load of 10 k
.
9. Gain temperature coefficient is given by: EG TC = [EG (Tmax)
Eg (Tmin)]/2Vref
×
106/(Tmax
Tmin).
output specifications
PARAMETER
TEST CONDITIONS
RL = 10 k
VO = 4.096 V, 2.048 V,
RL = 2 k
to 10
k
MIN
TYP
MAX
UNIT
VO
Output voltage range
0
VDD
0.4
V
Output load regulation accuracy
±
0.29
% FS
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