參數(shù)資料
型號: TLV5614(中文)
廠商: Texas Instruments, Inc.
英文描述: 2.7V to 5.5V 12-Bit 3us Quadruple Digital-to-Analog Converters With Power Down(具有掉電功能的2.7V至5.5V,12位,3微秒,四路DAC)
中文描述: 2.7V至5.5V 12位3us四倍數(shù)字模擬轉(zhuǎn)換器由于斷電(具有掉電功能的為2.7V至5.5V之間,12位,3微秒,四路援會)
文件頁數(shù): 6/20頁
文件大?。?/td> 529K
代理商: TLV5614(中文)
==1999-3-18==
P&S
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==20-5==
P &S
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μ :
ot±±ooêD×μèa· 15o
P&Sí í :
http://www.p8s.com
D :
ooêD70020D
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430079
μ°:
( 86) ( 027£87493500 87493506
( 86) ( 027) 87491166, 87493497
2.3.7
ê±Dòí
êy×êèê±Dòòó
í
1
ê±Dòí
2.4
μDí ìDú
0.2
VDD = 3 V,
Vref = 1 V,
VO = Full Scale
í
2
oμ÷ìD
í
3
oμ÷ìD
MIN
10
NOM
MAX
UNIT
ns
tsu(CS FS)
tsu(FS CK)
Setup time, CS low before FS
Setup time, FS low before first negative SCLK edge
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS
8
ns
tsu(C16 FS)
10
ns
tsu(C16 CS)
Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
10
ns
twH
twL
tsu(D)
th(D)
twH(FS)
Pulse duration, SCLK high
Pulse duration, SCLK low
25
25
ns
ns
Setup time, data ready before SCLK falling edge
8
ns
Hold time, data held valid after SCLK falling edge
5
ns
Pulse duration, FS high
20
ns
1 2
3
4
5
15
16
D15
D14
D13
D12
D1
D0
t
su( FS-CK)
tsu( CS-FS)
t
wHFS)
th(D)
t
su( D)
twH
twL
tsu( C16-CS)
tsu( C16-FS)
SCLK
DIN
CS
FS
0.12
0.08
0.04
0
0
0.01 0.02 0.05
0.1
0.2
0.5
VO
0.14
0.18
Load Current mA
1 2
0.16
0.10
0.06
0.02
3 V Slow Mode, Sink
3 V Fast Mode, Sink
0.20
0.15
0.05
0
0
0.02 0.04
0.1
0.2
0.4
1
0.25
0.30
0.35
2 4
0.10
VO
Load Current mA
VDD = 5 V,
Vref = 2 V,
VO = Full Scale
5 V Slow Mode, Sink
5 V Fast Mode, Sink
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