參數(shù)資料
型號： TLV320AIC3111IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 152/156頁
文件大?。?/td> 1701K
代理商： TLV320AIC3111IRHBT
www.ti.com
SLAS644B – JULY 2009 – REVISED OCTOBER 2009
Page 0 / Register 66: DAC Right Volume Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
127 to 49: Reserved. Do not write these sequences to these bits.
48: Right-channel DAC digital gain = 24 dB
47: Right-channel DAC digital gain = 23.5 dB
46: Right-channel DAC digital gain = 23 dB
...
36: Right-channel DAC digital gain = 18 dB
35: Right-channel DAC digital gain = 17.5 dB
34: Right-channel DAC digital gain = 17 dB
...
1: Right-channel DAC digital gain = 0.5 dB
0: Right-channel DAC digital gain = 0 dB
–1: Right-channel DAC digital gain = –0.5 dB
...
–126: Right-channel DAC digital gain = –63 dB
–127: Right-channel DAC digital gain = –63.5 dB
–128: Reserved
Page 0 / Register 67: Headset Detection
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Headset detection disabled
1: Headset detection enabled
D6–D5
R
XX
00: No headset detected
01: Headset without microphone is detected
10: Reserved
11: Headset with microphone is detected
D4–D2
R/W
000
Debounce Programming for Glitch Rejection During Headset Detection(1)
000: 16 ms (sampled with 2-ms clock)
001: 32 ms (sampled with 4-ms clock)
010: 64 ms (sampled with 8-ms clock)
011: 128 ms (sampled with 16-ms clock)
100: 256 ms (sampled with 32-ms clock)
101: 512 ms (sampled with 64-ms clock)
110: Reserved
111: Reserved
D1–D0
R/W
00
Debounce Programming for Glitch Rejection During Headset Button-Press Detection
00: 0 ms
01: 8 ms (sampled with 1-ms clock)
10: 16 ms (sampled with 2-ms clock)
11: 32 ms (sampled with 4-ms clock)
(1)
Note that these times are generated using the 1 MHz reference clock which is defined in page 3 / register 16.
Page 0 / Register 68: DRC Control 1
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Reserved. Write only the reset value to these bits.
D6
R/W
0
0: DRC disabled for left channel
1: DRC enabled for left channel
D5
R/W
0
0: DRC disabled for right channel
1: DRC enabled for right channel
D4–D2
R/W
011
000: DRC threshold = –3 dB
001: DRC threshold = –6 dB
010: DRC threshold = –9 dB
011: DRC threshold = –12 dB
100: DRC threshold = –15 dB
101: DRC threshold = –18 dB
110: DRC threshold = –21 dB
111: DRC threshold = –24 dB
D1–D0
R/W
11
00: DRC hysteresis = 0 dB
01: DRC hysteresis = 1 dB
10: DRC hysteresis = 2 dB
11: DRC hysteresis = 3 dB
Copyright 2009, Texas Instruments Incorporated
REGISTER MAP
95
Product Folder Link(s): TLV320AIC3111
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