參數(shù)資料
型號(hào)： TLV320AIC28IRGZG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC48
封裝： 7 X 7 MM, GREEN, PLASTIC, QFN-48
文件頁數(shù)： 13/85頁
文件大?。?/td> 1053K
代理商： TLV320AIC28IRGZG4
TLV320AIC28
SLAS418B FEBRUARY 2004 REVISED MAY 2005
www.ti.com
20
D Left Justified Mode
In left-justified mode, the MSB of right channel is valid on the rising edge of BCLK, following the falling edge on
WCLK. Similarly the MSB of left channel is valid on the rising edge of BCLK following the rising edge of
WCLK.
BCLK
WCLK
SDIN/
SDOUT
n
n1
1
0
n
n1
1
0
1/fs
LSB
MSB
Left Channel
Right Channel
n
n1
n2
2
n2
2
Figure 16. Timing Diagram for Left-Justified Mode
D I2S Mode
In I2S mode, the MSB of left channel is valid on the second rising edge of BCLK, after the falling edge on
WCLK. Similarly the MSB of right channel is valid on the second rising edge of BCLK, after the rising edge of
WCLK.
BCLK
WCLK
SDIN/
SDOUT
n
n1
1
0
n
n1
1
0
1/fs
LSB
MSB
Left Channel
Right Channel
n
1 clock before MSB
n2
2
n2
2
Figure 17. Timing Diagram for I2S Mode
D DSP Mode
In DSP mode, the falling edge of WCLK starts the data transfer with the left channel data first and immediately
followed by the right channel data. Each data bit is valid on the falling edge of BCLK.
BCLK
WCLK
SDIN/
SDOUT
n
n1
1
0
n
n1
1
0
1/fs
LSB
MSB
Left Channel
Right Channel
n
n1
1
0
MSB
LSB
n2
2
n2
2
n2
MSB
LSB
Figure 18. Timing Diagram for DSP Mode
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