TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
35
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register 3Eh – extended-modem status control (continued)
Bits 15 to 8 are read/write and control modem AFE subsystem power down. The TLV320AIC27 power-up/down
functions are entirely controlled from register 26h. However, the following registers are aliased onto the
appropriate control bits in registers 26h.
D PRA = 1 indicates GPIO power down
D PRB = 1 indicates modem VREF off – no separate modem VREF on TLV320AIC27, aliases from PR3
D PRC = 1 indicates modem line1 ADC off – aliases from PR0
D PRD = 1 indicates modem line1 DAC off – aliases from PR1
D PRE = 1 indicates modem line2 ADC off – not supported on TLV320AIC27
D PRF = 1 indicates modem line2 DAC off – not supported on TLV320AIC27
D PRG = 1 indicates handset ADC off – not supported on TLV320AIC27
D PRH = 1 indicates handset DAC off – not supported on TLV320AIC27
Bits 7 to 0 are read-only: a 1 indicates modem AFE subsystem readiness. Bits 15 to 8 are read/write and control
modem AFE subsystem power down. Writing ENABLES (0) to the above aliased PR bits is allowed, and will
write enable to the appropriate PRN bit. However, writing DISABLES (1) is not allowed.
register 40h – line1 ADC/DAC sample rate
The read/write register 40h controls the modem DAC and ADC sample rates. This register is only functional if
modem mode1 = 1 is selected from pins 30 and 40. The ADC only uses this sample rate if the input to the record
mux is also selected, as the right ADC in register 1Ah is PHONE. Note that only the recommended sample rates
are supported. If alternative sample rates are selected, the rate defaults to the nearest sample rate supported,
and that value is read back.
register 46h to 48h – line1 and line2 ADC level
These registers are not supported in TLV320AIC27. Register 04h is used to control TX modem level.
register 56h – miscellaneous modem AFE status/control
This read/write register defines the loop-back modes available for the modem line and handset ADCs/DACs
described in the Intel specification. Line1 ADC loopback-mode 001 L1B0 is supported.
GPIO function
Note that only GPIO pins 11 to 13 are supported. These pins are available to the user, unless used for I2S mode.
The GPIO mode overrides the I2S function.
register 4Ch – GPIO pin-configuration register
The GPIO pin configuration register is a read/write register that specifies whether a GPIO pin is configured for
input (1), or for output (0), and is accessed via the standard slots 1 and 2 command address/data protocols.
If a GPIO pin is implemented, the respective GCx bit should be readable/writeable and set to 1. If a GPIO is not
implemented, then the respective GCx bit is read-only and set to 0. This informs the software how many GPIO
pins have been implemented. It is up to the AC’97 digital controller to send the desired GPIO pin value over
output slot 12 in the outgoing stream of the ac link before configuring any of these bits for output. The default
value of this register (3800h) after cold reset or register reset is all pins configured as inputs.