參數(shù)資料
型號： TLV320AIC25IPFBRG4
廠商： Texas Instruments, Inc.
英文描述： Layout and Grounding Guidelines for TLV320AIC2x
中文描述： 為TLV320AIC2x布局和接地指南
文件頁數(shù)： 30/46頁
文件大?。?/td> 452K
代理商： TLV320AIC25IPFBRG4
SLAS428 AUGUST 2004
www.ti.com
30
REGISTER 02H: DAC Gain Control (continued)
BIT
NAME
READ/
WRITE
RESET
VALUE
FUNCTION
D7
DARMU
R/W
1
DAC Right Channel Muted
1 => DAC right channel muted
0 => DAC right channel not muted
D6D0
DARVL
R/W
1111111
DAC Right Channel Volume Control
0000000 => DAC right channel volume control = 0 dB
0000001 => DAC right channel volume control = 0.5 dB
0000010 => DAC right channel volume control = 1.0 dB
1111110 => DAC right channel volume control = 63.0 dB
1111111 => DAC right channel volume control = 63.5 dB
REGISTER 03H: Analog Sidetone Control
BIT
NAME
READ/
WRITE
RESET
VALUE
FUNCTION
D15
ASTMU
R/W
1
Analog Sidetone Mute Control
1 => Analog sidetone muted
0 => Analog sidetone not muted
D14D8
ASTG
R/W
1000101
Analog Sidetone Gain Setting
0000000 => Analog sidetone gain setting = 34.5 dB
0000001 => Analog sidetone gain setting = 34 dB
0000010 => Analog sidetone gain setting = 33.5 dB
1000101 => Analog sidetone gain setting = 0 dB
1000110 => Analog sidetone gain setting = 0.5 dB
1011100 => Analog sidetone gain setting = 11.5 dB
1011101 => Analog sidetone gain setting = 12 dB
1011110 => Analog sidetone gain setting = 12 dB
1011111 => Analog sidetone gain setting = 12 dB
11xxxxx => Analog sidetone gain setting = 12 dB
Reserved
Note: Only write a 1 to this bit
D7D1
Reserved
R/W
1
D0
ASTGF
R
0
Analog Sidetone PGA Flag ( Read Only )
0 => Gain applied /= PGA register setting
1 => PGA applied = PGA register setting.
Note: Analog sidetone gain is implemented at zero crossings of the signal.
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