參數(shù)資料
型號: TLV320AIC25IPFBR
廠商: Texas Instruments, Inc.
英文描述: Layout and Grounding Guidelines for TLV320AIC2x
中文描述: 為TLV320AIC2x布局和接地指南
文件頁數(shù): 7/46頁
文件大小: 452K
代理商: TLV320AIC25IPFBR
SLAS428 AUGUST 2004
www.ti.com
7
SPI TIMING DIAGRAM
ttd
ta
tsck
ten1
ten2
tw(swk)
tw(swk)
tr
tf
tv
th2
tdis
th1
tsu
SS
SCLK
MISO
MOSI
MSB OUT
BIT . . . 1
LSB OUT
MSB OUT
BIT . . . 1
LSB OUT
TYPICAL TIMING REQUIREMENTS
All specifications at 25
°
C, DVDD = 1.8 V (1)
PARAMETER
IOVDD = 1.1 V
MIN
27
IOVDD = 3.3 V
MIN
18
UNITS
MAX
MAX
tw(sck)
ten1
ten2
td
ta
tdis
tsu
th1
th2
tv
tr
tf
(1)These parameters are based on characterization and are not tested in production.
SCLK pulse width
ns
Enable lead time
18
15
ns
Enable lag time
18
15
ns
Sequential transfer delay time
18
15
ns
Slave MISO access time
18
15
ns
Slave MISO disable time
18
15
ns
MOSI data setup time
6
6
ns
MOSI data hold time
6
6
ns
MISO data hold time
4
4
ns
MISO data valid time
22
13
ns
Rise time
6
4
ns
Fall time
6
4
ns
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