參數(shù)資料
型號: TLV320AIC14C
廠商: Texas Instruments, Inc.
英文描述: PRODUCT NOTIFICATION
中文描述: 產(chǎn)品公告
文件頁數(shù): 10/46頁
文件大小: 452K
代理商: TLV320AIC14C
SLAS428 AUGUST 2004
www.ti.com
10
LRCK/ADWS
BCLK
DIN
tL(BCLK)
th(DI)
tS(WS)
tH(BCLK)
th(WS)
tP(BCLK)
th(WS)
tS(WS)
Figure 4. DSP Timing in Slave Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 4)
All specifications at 25
°
C, DVDD = 1.8 V (1)
PARAMETER
IOVDD = 1.1 V
MIN
35
IOVDD = 3.3 V
MIN
35
UNITS
MAX
MAX
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
ts(DI)
th(DI)
tr
tf
(1)These parameters are based on characterization and are not tested in production.
BCLK high period
ns
BCLK low period
35
35
ns
LRCK setup time
6
6
ns
LRCK hold time
6
6
ns
DIN setup time
6
6
ns
DIN hold time
6
6
ns
Rise time
5
4
ns
Fall time
5
4
ns
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