- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371186 > TLV320AC56N (Texas Instruments, Inc.) 3-V VOICE-BAND AUDIO PROCESSORS VBAPE PDF資料下載
參數(shù)資料
| 型號： | TLV320AC56N |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3-V VOICE-BAND AUDIO PROCESSORS VBAPE |
| 中文描述： | 3伏的語音頻帶音頻處理器VBAPE |
| 文件頁數(shù)： | 24/46頁 |
| 文件大?。?/td> | 452K |
| 代理商： | TLV320AC56N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
SLAS428 AUGUST 2004
www.ti.com
24
SPI DIGITAL INTERFACE
All ’DAC26 control registers are programmed through a standard SPI bus. The SPI allows full-duplex, synchronous, serial
communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the
synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize
transmissions.
A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the slave SPIDIN
(MOSI) pin under the control of the master serial clock. As the byte shifts in on the SPIDIN pin, a byte shifts out on the
SPIDOUT (MISO) pin to the master shift register.
The idle state of the serial clock for the ’DAC26 is low, which corresponds to a clock polarity setting of 0 (typical
microprocessor SPI control bit CPOL = 0). The ’DAC26 interface is designed so that with a clock phase bit setting of 1
(typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its
SPIDOUT pin on the first serial clock edge. The SS pin can remain low between transmissions; however, the ’DAC26 only
interprets command words which are transmitted after the falling edge of SS.
Hardware Reset
The device requires a low-to-high pulse on RESET after power up for correct operation. A hardware reset pulse initializes
all the internal registers, counters, and logic.
Hardware Power Down
By default the PWD pin is configured as a hardware power-down (active low) signal. The device powers down all the internal
circuitry to save power. All the register contents are maintained. Some counters maintain their value.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLV320AC56PT | 3-V VOICE-BAND AUDIO PROCESSORS VBAPE |
| TLV320AIC20I | Layout and Grounding Guidelines for TLV320AIC2x |
| TLV320AIC10PFB | ECONOLINE: RSS & RSD - 1kVDC and 3KVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 85%- SMD5, SMD8, SMD10 and SMD12 case styles |
| TLV320AC57DW | 3-V VOICE-BAND AUDIO PROCESSORS VBAPE |
| TLV320AIC24C | Layout and Grounding Guidelines for TLV320AIC2x |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320AC56PT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V VOICE-BAND AUDIO PROCESSORS VBAPE |
| TLV320AC57 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V VOICE-BAND AUDIO PROCESSORS VBAPE |
| TLV320AC57DW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V VOICE-BAND AUDIO PROCESSORS VBAPE |
| TLV320AC57N | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V VOICE-BAND AUDIO PROCESSORS VBAPE |
| TLV320AC57PT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V VOICE-BAND AUDIO PROCESSORS VBAPE |
發(fā)布緊急采購，3分鐘左右您將得到回復。