參數(shù)資料
型號(hào): TLV2541CDGKRG4
廠商: Texas Instruments
文件頁(yè)數(shù): 3/32頁(yè)
文件大小: 0K
描述: IC 12BIT 200 KSPS ADC S/O 8-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 200k
數(shù)據(jù)接口: DSP,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.8mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 1 個(gè)單端,單極
配用: 296-20577-ND - EVAL MOD FOR TLV2541
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E MARCH 2000 REVISED APRIL 2010
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
ac specifications (fi = 20 kHz)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SINAD
Signal to noise ratio +distortion
200 KSPS, VDD = VREF = 5.5 V
70
72
dB
SINAD
Signal-to-noise ratio +distortion
150 KSPS, VDD = VREF = 2.7 V
68
71
dB
THD
Total harmonic distortion
200 KSPS, VDD = VREF = 5.5 V
84
80
dB
THD
Total harmonic distortion
150 KSPS, VDD = VREF = 2.7 V
84
80
dB
ENOB
Effective number of bits
200 KSPS, VDD = VREF = 5.5 V
11.8
Bits
ENOB
Effective number of bits
150 KSPS, VDD = VREF = 2.7 V
11.6
Bits
SFDR
Spurious free dynamic range
200 KSPS, VDD = VREF = 5.5 V
84
80
dB
SFDR
Spurious free dynamic range
150 KSPS, VDD = VREF = 2.7 V
84
80
dB
Analog Input
Full-power bandwidth, 3 dB
1
MHz
Full-power bandwidth, 1 dB
500
kHz
external reference specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference input voltage
VDD = 2.7 V to 5.5 V
2
VDD
V
55 V
CS = 1, SCLK = 0
100
Reference input impedance
VDD = 5.5 V
CS = 0, SCLK = 20 MHz
20
25
Reference input impedance
V
27 V
CS = 1, SCLK = 0
100
VDD = 2.7 V
CS = 0, SCLK = 20 MHz
20
25
Reference current
VDD = VREF = 5.5 V,
CS = 0, SCLK = 20 MHz
100
400
μA
Reference current
VDD = VREF = 2.7 V,
CS = 0, SCLK = 20 MHz
50
200
μA
V
55 V
CS = 1, SCLK = 0
5
15
Reference input capacitance
VDD = VREF = 5.5 V
CS = 0, SCLK = 20 MHz
20
45
50
pF
Reference input capacitance
V
27 V
CS = 1, SCLK = 0
5
15
pF
VDD = VREF = 2.7 V
CS = 0, SCLK = 20 MHz
20
45
50
VREF
Reference voltage
VDD = 2.7 V to 5.5 V
VDD
V
dc specification, VDD = VREF = 2.7 V to 5.5 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INL
Integral linearity error (see Note 4)
±0.6
±1
LSB
DNL
Differential linearity error
See Note 3
±0.5
±1
LSB
E
Offset error (see Note 5)
See Note 3
TLV2541/42
±1.5
LSB
EO
Offset error (see Note 5)
See Note 3
TLV2545
±2.5
LSB
E
Gain error (see Note 5)
See Note 3
TLV2541/42
±2
LSB
EG
Gain error (see Note 5)
See Note 3
TLV2545
±5
LSB
E
Total unadjusted error (see Note 6)
See Note 3
TLV2541/42
±2
LSB
Et
Total unadjusted error (see Note 6)
See Note 3
TLV2545
±5
LSB
NOTES: 3. Analog input voltages greater than that applied to VREF convert as all ones (111111111111).
4. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.
5. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference
between 111111111111 and the converted output for full-scale input voltage.
6. Total unadjusted error comprises linearity, zero, and full-scale errors.
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