參數(shù)資料
型號： TLV2262MJG
廠商： Texas Instruments, Inc.
英文描述： FITTING FOR TYPE LDP SURFACE RACEWAY, INSIDE CORNER, USE WITH LDP3 RoHS Compliant: Yes
中文描述： 高級LinCMOSE軌至軌運(yùn)算放大器
文件頁數(shù)： 41/51頁
文件大小： 817K
代理商： TLV2262MJG
TLV226x, TLV226xA
Advanced LinCMOS
RAIL-TO-RAIL
OPERATIONAL AMPLIFIERS
SLOS186A – FEBRUARY 1997 – REVISED JULY 1999
41
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts
, the model generation software used
with Microsim PSpice
. The Boyle macromodel (see Note 5) and subcircuit in Figure 62 are generated using
the TLV226x typical electrical and operating characteristics at T
A
= 25
°
C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers,” IEEE
Journal of Solid-State Circuits,SC-9, 353 (1974).
OUT
+
–
+
–
53
+
–
+
–
+
–
+
–
+
–
+
–
+
–
.SUBCKT TLV226x 1 2 3 4 5
C1
11
C2
6
DC
5
DE
54
DLP
90
DLN
92
DP
4
EGND
99
FB
7
+ VLN 0 8.84E6 –10E6 10E6 10E6 –10E6
GA
6
0
GCM
0
6
ISS
3
10
HLIM
90
0
J1
11
2
J2
12
1
R2
6
9
12
7
53
5
91
90
3
0
99
5.5E–12
20.00E–12
DX
DX
DX
DX
DX
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
11
10
DC 11.05E–6
VLIM 1K
10 JX
10 JX
100.0E3
12 62.83E–6
99 12.34E–9
RD1
RD2
R01
R02
RP
RSS
VAD
VB
VC
VE
VLIM
VLP
VLN
.MODEL DX D (IS=800.0E–18)
.MODEL JX PJF (IS=500.0E–15 BETA=325E–6
+ VTO=–.08)
.ENDS
60
60
8
7
3
10
60
9
3
54
7
91
0
11
12
5
99
4
99
4
0
53
4
8
0
92
15.92E3
15.92E3
135
135
15.87E3
18.18E6
–.5
DC 0
DC .615
DC .615
DC 0
DC 1
DC 5.1
VCC+
RP
IN –
2
IN+
1
VCC–
VAD
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
60
VE
54
DE
DP
VC
DC
4
C1
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DLP
91
DLN
92
VLN
VLP
99
7
Figure 62. Boyle Macromodel and Subcircuit
PSpice and Partsare trademarks of MicroSim Corporation.
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