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參數(shù)資料
| 型號(hào)： | TLV1549IP |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 4/19頁(yè) |
| 文件大小： | 0K |
| 描述： | IC 10 BIT 38 KSPS ADC S/O 8-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 38k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.32mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)單端，單極 |
| 產(chǎn)品目錄頁(yè)面： | 897 (CN2011-ZH PDF) |
| 其它名稱： | 296-2965-5 |
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TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071C – JANUARY 1993 – REVISED MARCH 1995
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Sample Cycle B
A/D Conversion
Interval
(
≤ 21 μs)
Initialize
MSB
LSB
Previous Conversion Data
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Low Level
12
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
CS
Initialize
Must Be High on Power Up
14
15
16
See Note C
(see Note A)
Figure 9. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed Within 21
μs)
Sample Cycle B
Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
12
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
CS
Initialize
11
Hi-Z State
16
Low
Level
(see Note A)
(
≤ 21 μs)
A/D
See Note B
Figure 10. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed After 21
μs)
Sample Cycle B
A/D Conversion Interval
Initialize
MSB
LSB
Previous Conversion Data
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
12
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
CS
Must Be High on Power Up
14
15
16
See Note C
See Note B
Low Level
(see Note A)
(
≤ 21 μs)
Figure 11. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed After 21
μs)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system
clock after CS
↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock.
C. The first I/O CLOCK must occur after the end of the previous conversion.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV1549IPE4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 38 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV1549M | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| TLV1549MFK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| TLV1549MJG | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| TLV1562 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN |
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