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參數(shù)資料
| 型號： | TLV1549IDR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 19/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SER 38K 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 38k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.32mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071C – JANUARY 1993 – REVISED MARCH 1995
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Linearity error (see Note 6)
±1
LSB
Zero error (see Note 7)
See Note 2
±1
LSB
Full-scale error (see Note 7)
See Note 2
±1
LSB
Total unadjusted error (see Note 8)
±1
LSB
tconv
Conversion time
See Figures 6 – 11
21
μs
tc
Total cycle time (access, sample, and conversion)
See Figures 6 – 11
and Note 9
21
+ 10 I/O
CLOCK
periods
μs
tv
Valid time, DATA OUT remains valid after I/O CLOCK
↓
See Figure 5
10
ns
td(I/O-DATA) Delay time, I/O CLOCK↓ to DATA OUT valid
See Figure 5
240
ns
tPZH, tPZL
Enable time, CS
↓ to DATA OUT (MSB driven)
See Figure 3
1.3
μs
tPHZ, tPLZ
Disable time, CS
↑ to DATA OUT (high impedance)
See Figure 3
180
ns
tr(bus)
Rise time, data bus
See Figure 5
300
ns
tf(bus)
Fall time, data bus
See Figure 5
300
ns
td(I/O-CS)
Delay time, 10th I/O CLOCK
↓ to CS↓ to abort conversion (see Note10)
9
μs
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF – convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ – Vref–); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A / D transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero, and full-scale errors.
9. I/O CLOCK period = 1/(I/O CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven
I/O CLOCK periods, and ends on the falling edge of the tenth I/O CLOCK (see Figure 5).
10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of
the internal clock (1.425
μs) after the transition.
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| TLV1549M | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| TLV1549MFK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
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