參數(shù)資料
型號(hào)： TLV1548QDBRQ1
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： ADC
英文描述： 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： ROHS COMPLIANT, PLASTIC, SSOP-20
文件頁(yè)數(shù)： 34/34頁(yè)
文件大小： 532K
代理商： TLV1548QDBRQ1
TLV1548Q1
LOW VOLTAGE 10BIT ANALOGTODIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
SGLS172B JUNE 2003 REVISED APRIL 2008
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
extended sampling, asynchronous start of sampling: CSTART operation
The extended sampling mode of operation programs the acquisition time (tACQ) of the sample-and-hold circuit.
This allows the analog inputs of the device to be directly interfaced to a wide range of input source impedances.
The extended sampling mode consumes higher power depending on the duration of the sampling period
chosen.
CSTART controls the sampling period and starts the conversion. The falling edge of CSTART initiates the
sampling period of a preset channel. The low time of CSTART controls the acquisition time of the input
sample-and-hold circuit. The sample is held on the rising edge of CSTART. Asserting CSTART causes the
converter to perform a new sample of the signal on the preset valid MUX channel (one of the eight) and discard
the current conversion result ready for output. Sampling continues as long as CSTART is active (negative). The
rising edge of CSTART ends the sampling cycle. The conversion cycle starts two internal system clocks after
the rising edge of CSTART.
Once the conversion is complete, the processor can initiate a normal I/O cycle to read the conversion result and
set the MUX address for the next conversion. Since the internal flag AsyncFlag is set high, this flag setting
indicates the cycle is an output cycle, so no conversion is performed during the cycle. The internal state machine
tests the AsyncFlag on the falling edge of CS. AsyncFlag is set high at the rising edge of CSTART, and it is reset
low at the rising edge of each CS. A conversion cycle follows a sampling cycle only if AsyncFlag is tested as
low at the falling edge of CS. As shown in Figure 2, an asynchronous I/O cycle can be removed by two
consecutive normal I/O cycles.
Table 4. TLV1548 Hardware Configuration for Different Operating Modes
OPERATING MODES
CS
CSTART
AsyncFlag at CS
↓
ACTION
Normal sampling
Low
High
Low
Fixed 6 I/O CLK sampling, synchronous conversion follows
Normal I/O (read out only)
Low
High
No sampling, no conversion
Extended sampling
High
Low
N/A
Flexible sampling period controlled by CSTART,
asynchronous conversion follows
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV1549 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
TLV1549C 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
TLV1549CD 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 3.3V 10bit A/D RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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TLV1549CDR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 38 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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