參數(shù)資料
型號(hào)： TLV1548MFK
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC20
封裝： CERAMIC, LCC-20
文件頁(yè)數(shù)： 31/36頁(yè)
文件大?。?/td> 676K
代理商： TLV1548MFK
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
I/O CLK
3
18
I
Input/output clock. I/O CLK receives the serial I/O clock input in the two modes and performs the following
four functions in each mode:
Microprocessor mode
WhenINVCLK=V
CC, I/O CLK clocks the four input data bits into the input data register on the first four
rising edges of I/O CLK after CS
↓ with the multiplexer address available after the fourth rising edge.
When INV CLK = GND, input data bits are clocked in on the first four falling edges instead.
On the fourth falling edge of I/O CLK, the analog input voltage on the selected multiplex input begins
charging the capacitor array and continues to do so until the tenth rising edge of I/O CLK except in the
extended sampling cycle where the duration of CSTART determines when to end the sampling cycle.
Output data bits change on the first ten falling I/O clock edges regardless of the condition of INV CLK.
I/O CLK transfers control of the conversion to the internal state machine on the tenth rising edge of I/O
CLK regardless of the condition of INV CLK.
Digital signal processor (DSP) mode
WhenINVCLK=V
CC, I/O CLK clocks the four input data bits into the input data register on the first four
falling edges of I/O CLK after FS
↓ with the multiplexer address available after the fourth falling edges.
When INV CLK = GND, input data bits are clocked in on the first four rising edges instead.
On the fourth rising edge of I/O CLK, the analog input voltage on the selected multiplex input begins
charging the capacitor array and continues to do so until the tenth falling edge of I/O CLK except in the
extended sampling cycle where the duration of CSTART determines when to end the sampling cycle.
Output data MSB shows after FS↓and the rest of the output data bits change on the first ten rising I/O
CLK edges regarless of the condition of INV CLK.
I/OCLKtransferscontroloftheconversiontotheinternalstatemachineonthetenthfallingedgeofI/O
CLK regardless of the condition of INV CLK.
REF+
15
14
I
Upper reference voltage (nominally VCC ). The maximum input voltage range is determined by the difference
between the voltages applied to REF+ and REF–.
REF–
14
13
I
Lower reference voltage (nominally ground)
VCC
5
20
I
Positive supply voltage
Terminal numbers are for the D package.
Terminal numbers are for the DB, J, and FK packages.
detailed description
Initially, with CS high (inactive), DATA IN and I/O CLK are disabled and DATA OUT is in the high-impedance
state. When the serial interface takes CS low (active), the conversion sequence begins with the enabling of I/O
CLK and DATA IN and the removal of DATA OUT from the high-impedance state. The host then provides the
4-bit channel address to DATA IN and the I/O clock sequence to I/O CLK. During this transfer, the host serial
interface also receives the previous conversion result from DATA OUT. I/O CLK receives an input sequence from
the host that is from 10 to 16 clocks long. The first four valid I/O CLK cycles load the input data register with the
4-bit input data on DATA IN that selects the desired analog channel. The next six clock cycles provide the control
timing for sampling the analog input. Sampling of the analog input is held after the first valid I/O CLK sequence
of ten clocks. The tenth clock edge also takes EOC low and begins the conversion. The exact locations of the
I/O clock edges depend on the mode of operation.
serial interface
The TLV1548 is compatible with generic microprocessor serial interfaces such as SPI and QSPI, and a TMS320
DSP serial interface. The internal latched flag If_mode is generated by sampling the state of FS at the falling
edge of CS. If_mode is set to one (for microprocessor) when FS is high at the falling edge of CS, and If_mode
is cleared to zero (for DSP) when FS is low at the falling edge of CS. This flag controls the multiplexing of I/O
CLK and the state machine reset function. FS is pulled high when interfacing with a microprocessor.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV1548MFKB 制造商:TI 制造商全稱:Texas Instruments 功能描述:LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
TLV1548MJ 制造商:TI 制造商全稱:Texas Instruments 功能描述:LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
TLV1548MJB 制造商:Rochester Electronics LLC 功能描述:- Bulk
TLV1548-Q1 制造商:TI 制造商全稱:Texas Instruments 功能描述:LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 8 ANALOG INPUTS
TLV1548QDBREP 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Lo Vltg 10B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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