參數(shù)資料
型號: TLV1543IDBG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, SSOP-20
文件頁數(shù): 7/29頁
文件大?。?/td> 804K
代理商: TLV1543IDBG4
TLV1543C, TLV1543I, TLV1543M
3.3V 10BIT ANALOGTODIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072E DECEMBER 1992 REVISED JANUARY 2004
15
WWW.TI.COM
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system
clock after CS
↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum
chip CS setup time has elapsed.
B. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial
interface synchronization.
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B3
B2
B1
B0
C3
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
12
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
11
Hi-Z State
16
See Note B
Low
Level
(see Note A)
Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B3
B2
B1
B0
C3
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
12
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Must be High on Power Up
14
15
16
See Note B
See Note A
Low Level
Access Cycle B
(see Note A)
Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)
NOTES: A. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial
interface synchronization.
B. The I/O CLOCK sequence is exactly 16 clock pulses long.
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