參數(shù)資料
型號: TLE8242-2
廠商: INFINEON TECHNOLOGIES AG
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, LQFP-144
文件頁數(shù): 24/78頁
文件大?。?/td> 1589K
代理商: TLE8242-2
TLE8242-2
Functional Description and Electrical Characteristics
Data Sheet
30
Rev. 1.0, 2010-02-09
5.7
Direct PWM control
In Direct PWM control mode, the PI control loop is disabled. The integrator in the constant current control logic is
cleared and held at 0 while direct PWM mode is active. The frequency and duty cycle of the OUTx pin signal is
directly controlled via SPI messages.
5.7.1
Selecting the Frequency of Operation
The period of the PWM is programmed in whole numbers of clocks from the CLK input (as in constant current
mode). The following formula is applied:
or
The value N is the divider programmed via the SPI interface. The IC will automatically limit the lower value of N to
79. If a value lower than 79 is programmed, the IC shall default N for that channel to 79 and return a value of 79
in the SPI response. The maximum value of N is 214-1 as it is programmed as a 14-bit number via SPI.
If a new value of N is programmed during operation, the new value of N will be returned on the next SPI message,
and the new value of N will be used at the beginning of the next PWM cycle. The default value for N is 625.
The value of M is the number of A/D samples in one PWM period. M is programmed with the value 32, 64, 128,
or 512 via an SPI message. The default value for M is 32. The PWM frequency multiplied by the value M is the
analog to digital converter sample rate. This sample rate must be no greater than 128 KHz.
5.7.2
Selecting the Duty Cycle
The duty cycle of the PWM is also programmed in whole numbers of clocks from the CLK input. The following
formula is applied:
PWM duty cycle is a 19 bit value programmed in SPI message # 15 “PWM duty cycle”.
or
The maximum duty cycle is clipped to 100%
N
*
M
*
T
CLK
PWM =
N
*
M
f
CLK
PWM =
32
M
cycle
duty
PWM
*
T
CLK
ON
=
[]
100%
N
32
cycle
duty
PWM
%
Cycle
Duty
=
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