參數(shù)資料
型號： TLC7524IPWLE
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO16
封裝： SO-16
文件頁數(shù)： 11/13頁
文件大小： 220K
代理商： TLC7524IPWLE
TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
+
–
Output
RA = 2 k
(see Note A)
WR
CS
DB0–DB7
Vref
C (see Note B)
RB
VDD
GND
OUT2
OUT1
RFB
NOTES: A. RA and RB used only if gain adjustment is required.
B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent
ringing or oscillation.
Figure 3. Unipolar Operation (2-Quadrant Multiplication)
Output
20 k
5 k
10 k
20 k
–
+
+
–
RFB
OUT1
OUT2
GND
VDD
RB
C (see Note B)
Vref
DB0–DB7
CS
WR
(see Note A)
RA = 2 k
NOTES: A. RA and RB used only if gain adjustment is required.
B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.
Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 1. Unipolar Binary Code
Table 2. Bipolar (Offset Binary) Code
DIGITAL INPUT
(see Note 3)
ANALOG OUTPUT
DIGITAL INPUT
(see Note 4)
ANALOG OUTPUT
MSB
LSB
MSB
LSB
1 1 1 1 1 1 1 1
–Vref (255/256)
1 1 1 1 1 1 1 1
Vref (127/128)
1 0 0 0 0 0 0 1
–Vref (129/256)
1 0 0 0 0 0 0 1
Vref (1/128)
1 0 0 0 0 0 0 0
–Vref (128/256) = – Vref/2
1 0 0 0 0 0 0 0
0
0 1 1 1 1 1 1 1
–Vref (127/256)
0 1 1 1 1 1 1 1
–Vref (1/128)
0 0 0 0 0 0 0 1
–Vref (1/256)
0 0 0 0 0 0 0 1
–Vref (127/128)
0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0
–Vref
NOTE 3: LSB = 1/256 (Vref)
NOTE 4: LSB = 1/128 (Vref)
相關(guān)PDF資料
PDF描述
TLC7524CPWLE PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO16
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