參數(shù)資料
型號: TLC542I
廠商: Texas Instruments, Inc.
英文描述: 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS
中文描述: 8位模擬到數(shù)字與串行控制和11變換器輸入端
文件頁數(shù): 4/11頁
文件大?。?/td> 161K
代理商: TLC542I
TLC542C, TLC542I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions, V
CC
= 4.75 to 5.5 V
MIN
NOM
MAX
UNIT
Supply voltage, VCC
Positive reference voltage, Vref+ (see Note 2)
Negative reference voltage, Vref– (see Note 2)
Differential reference voltage, Vref+ – Vref– (see Note 2)
Analog input voltage (see Note 3)
4.75
5
5.5
V
Vref–
–0.1
VCC
VCC + 0.1
Vref+
VCC + 0.2
VCC
V
0
V
1
VCC
V
0
V
High-level control input voltage, VIH
Low-level control input voltage, VIL
Setup time, address bits at data input before I/O CLOCK
, tsu(A)
Hold time, address bits after I/O CLOCK
, th(A)
Hold time, CS low after 8th I/O CLOCK
, th(CS)
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 4)
Input/output clock frequency, fclock(I/O)
Input/output clock high, twH(I/O)
Input/output clock low, twL(I/O)
2
V
0.8
V
400
ns
0
ns
0
ns
μ
s
MHz
3.8
0
1.1
404
ns
404
ns
I/O CLOCK transition time tt(see Note 3)
I/O CLOCK transition time, tt (see Note 3)
fclock(I/O)
525 kHz
fclock(I/O) > 525 kHz
TLC542C
TLC542I
100
ns
40
Operating free air temperature TA
Operating free-air temperature, TA
0
70
85
°
C
–40
NOTES:
2. Analog input voltages greater than that applied to REF+ convert as all ones (11111111), while input voltages less than that applied
to REF– convert as all zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF–. Also, the total
unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2
μ
s for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
4. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two rising edges and one falling edge of
the internal system clock after CS
before responding to control input signals. The CS setup time is given by the tsu(CS)
specifications. Therefore, no attempt should be made to clock-in address data until the minimum chip select setup time has elapsed.
electrical characteristics over recommended operating temperature range, V
CC
= V
ref+
= 4.75 V to
5.5 V, f
clock(I/O)
= 1.1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
High-level output voltage (DATA OUT)
VCC = 4.75 V,
VCC = 4.75 V,
VO = VCC,
VO = 0,
VI = VCC
VI = 0
CS at 0 V
IOH = –360
μ
A
IOL = 1.6 mA
CS at VCC
CS at VCC
2.4
V
Low-level output voltage
0.4
V
Off-state (high-impedance state)
( g
output current
10
μ
A
–10
IIH
IIL
ICC
High-level input current
0.005
2
μ
A
μ
A
mA
Low-level input current
–0.005
–2.5
Operating supply current
1.2
2
Selected channel leakage current
Selected at VCC,
Unselected channel at 0 V
0
°
C to 70
°
C
– 40
°
C to 85
°
C
0.4
μ
A
–0.4
Iref
Maximum static analog reference current into
REF+
Vref+ = VCC,
Vref– = GND
10
μ
A
Ci
Input capacitance
Analog inputs
Control inputs
7
5
55
15
pF
All typical values are at TA = 25
°
C.
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