參數(shù)資料
型號: TLC542C
廠商: Texas Instruments, Inc.
英文描述: 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS
中文描述: 8位模擬到數(shù)字與串行控制和11變換器輸入端
文件頁數(shù): 5/11頁
文件大小: 161K
代理商: TLC542C
TLC542C, TLC542I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
V
CC
= V
ref+
= 4.75 to 5.5 V, f
clock(I/O)
= 1 MHZ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±
0.5
±
0.5
±
0.5
±
0.5
UNIT
EL
EZS
EFS
Linearity error (see Note 5)
LSB
Zero-scale error (see Note 6)
See Note 2
LSB
Full-scale error (see Note 6)
See Note 2
LSB
Total unadjusted error (see Note 7)
LSB
Self-test output code
Input A11 address = 1011,
See Note 8
01111101
(126)
128
10000011
(130)
tconv
tcycle
tacq
tv
td(IO-DATA)
td(IO-EOC)
td(EOC-DATA)
tPZH, tPZL
tPHZ, tPLZ
tr(EOC)
tf(EOC)
tr(bus)
tf(bus)
All typical values are at TA = 25
°
C
NOTES:
2. Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that applied
to REF– convert to all zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF–. Also, the total
unadjusted error may increase as this differential reference voltage falls below 4.75 V.
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Zero-scale Error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The A11 analog input signal is internally generated and
is used for test purposes.
Conversion time
See operating sequence
20
μ
s
μ
s
μ
s
ns
Total access and conversion cycle time
See operating sequence
40
Channel acquisition time (sample cycle)
Time ouput data remains valid after I/O CLK
Delay time, I/O CLK
to data output valid
Delay time, 8th I/O CLK
to EOC
Delay time, EOC
to data out (MSB)
Delay time, CS
to data out (MSB)
Delay time, CS
to data out (MSB)
Rise time
See operating sequence
16
See Figure 5
10
See Figure 5
400
ns
See Figure 6
500
ns
See Figure 7
400
ns
μ
s
ns
See Figure 2
3.4
See Figure 2
150
See Figure 7
100
ns
Fall time
See Figure 6
100
ns
Data bus rise time
See Figure 5
300
ns
Data bus fall time
See Figure 5
300
ns
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