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參數(shù)資料
| 型號： | TLC4541EVM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TLC4541EVM(TLC4541評估板) |
| 中文描述： | TLC4541EVM（TLC4541評估板） |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 155K |
| 代理商： | TLC4541EVM |
Analog Interface
1-4
1.4
Analog Interface
The EVM board is designed for easy interfacing to analog sources such as
signal generators and sensors. The buffer amplifier U1 is in a follower
configuration, non-inverting gain of one. Output of this buffer drives the AIN(+)
pin of the DUT through a 33- resistor (R4). If desired, the user can bypass
U1 by connecting pins 1-2 of jumper W2.
For low level common mode
rejection (< 0.2V P-P) dual input pseudo-differential devices TLC4545,
TLC3545, TLC2555 or TLV2545 can be used, byassing U1
.
Table 1-6.Analog Input Connector J1
Pin
Signal
Description
J1.1
AIN0
Analog input signal to the non-inverting input of U1
J1.3
-AIN0
Second input to dual and pseudo differential devices
J1.5
N/C
J1.7
N/C
J1.9
N/C
J1.11
N/C
J1.13
N/C
J1.15
N/C
J1.17
REF+
External refence voltage for the DUT
J1.19
N/C
1.5
Digital Interface
The EVM is designed for easy interfacing to multiple platforms. Samtec part
numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a
convenient 10-pin dual-row header and socket combination at P2. This
header/socket provides access to the digital control and serial data pins for all
10 of the 12-, 14-, and 16-bit ADCs. Consult Samtec at
www.samtec.com
or
1-800-SAMTEC-9 for a variety of mating connector options.
Table 1-7.Digital Connector J2
Pin Number
Signal
Description
J2.1
CS
Chip select
–
Active low signal, enables data transfer and device configuration
J2.3
CLKXa
Serial clock
—
damped with 33- resistor
J2.5
CLKRa
Serial Clock
J2.7
FSXa
Frame sync
—
damped with 33- resistor
J2.9
FSRa
Frame sync (see Note)
J2.11
Reserved
J2.13
DXRa
Serial data out
J2.15
Reserved
J2.17
Reserved
J2.19
Reserved
Note:
When using a single input ADC, TLC4541, TLC3541, TLC2551
or TLV2541, Frame Sync must be held at V
DD
.
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