參數(shù)資料
型號(hào)： TLC3578IPWRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封裝： GREEN, PLASTIC, TSSOP-24
文件頁(yè)數(shù)： 1/49頁(yè)
文件大?。?/td> 1137K
代理商： TLC3578IPWRG4
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SCLK
FS
SDI
EOC/INT
SDO
DGND
DVDD
CS
A0
A1
A2
A3
CSTART
AVDD
AGND
COMP
REFM
REFP
AGND
AVDD
A7
A6
A5
A4
TLC3578, TLC2578
DW OR PW PACKAGE
(TOP VIEW)
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SCLK
FS
SDI
EOC/INT
SDO
DGND
DVDD
CS
A0
A1
CSTART
AVDD
AGND
COMP
REFM
REFP
AGND
AVDD
A3
A2
TLC3574, TLC2574
DW, N, OR PW PACKAGE
(TOP VIEW)
TLC3574, TLC3578, TLC2574, TLC2578
5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL
SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS
SLAS262C OCTOBER 2000 REVISED MAY 2003
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WWW.TI.COM
D 14-Bit Resolution for TLC3574/78, 12-Bit for
TLC2574/2578
D Maximum Throughput 200-KSPS
D Multiple Analog Inputs:
8 Single-Ended Channels for
TLC3578/2578
4 Single-Ended Channels for
TLC3574/2574
D Analog Input Range: ±10 V
D Pseudodifferential Analog Inputs
D SPI/DSP-Compatible Serial Interfaces With
SCLK up to 25-MHz
D Built-In Conversion Clock and 8x FIFO
D Single 5-V Analog Supply; 3-/5-V Digital
Supply
D Low-Power
5.8 mA in Normal Operation
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A in Power Down
D Programmable Autochannel Sweep and
Repeat
D Hardware-Controlled, Programmable
Sampling Period
D Hardware Default Configuration
D INL: TLC3574/78: ±1 LSB;
TLC2574/78:
±0.5 LSB
D DNL: TLC3574/78: ±0.5 LSB;
TLC2574/78:
±0.5 LSB
D SINAD: TLC3574/78: 79 dB;
TLC2574/78: 72 dB
D THD: TLC3574/78: 82 dB;
TLC2574/78: 82 dB
description
The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS
analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate
from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital
input [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state
serial data output (SDO). CS (works as SS, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI,
SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being
transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow
the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must
be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in
hardware default mode after power on and no software configuration is required. In the simplest case, only three
wires (SDO, SCLK, and CS or FS) are needed to interface with the host.
Copyright
2000 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
相關(guān)PDF資料
PDF描述
TLC3578IPWR 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
TLC3574IPWG4 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLC2574IPWG4 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLC3578IDWR 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
TLC2574IDW 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
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