參數(shù)資料
型號: TLC3544IPWR
廠商: Texas Instruments, Inc.
英文描述: 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
中文描述: 5 - V模擬,3-/5-V數(shù)字,14位,200 kSPS的,4-/8-CHANNELS串行模數(shù)位0-5五(擬微分)輸入變換器
文件頁數(shù): 7/40頁
文件大?。?/td> 790K
代理商: TLC3544IPWR
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C
OCTOBER 2000
REVISED MAY 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
general electrical characteristics over recommended operating free-air temperature range,
single-ended input, normal long sampling, 200 KSPS, AV
DD
= 5 V, external reference (V
REFP
= 4 V,
V
REFM
= 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,
analog input signal source resistance = 25
(unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14
bits
Analog Input
Voltage range
0
Reference
V
μ
A
pF
Leakage current
0.01
0.05
Capacitance
30
Reference
Internal reference voltage
3.85
4
4.07
V
Internal reference temperature
coefficient
100
ppm/
°
C
Internal reference source current
1.8
2.5
mA
Internal reference startup time
20
ms
VREFP
VREFM
External positive reference voltage
3
5
V
External negative reference voltage
0
AGND
V
No conversion (AVDD = 5 V,
CS = DVDD, SCLK = DGND)
Normal long sampling (AVDD = 5 V,
CS = DGND, SCLK = 25 MHz,
External conversion clock)
100
M
External reference input impedance
8.3
12.5
k
External reference current
No conversion (VREFP = AVDD = 5 V,
VREFM = AGND, External reference,
CS = DVDD)
Normal long sampling (AVDD = 5 V,
CS = DGND, SCLK = 25 MHz external
conversion clock at VREF = 5 V)
1.5
μ
A
0.4
0.6
mA
Throughput Rate
f
Internal oscillation frequency
DVDD = 2.7 V to 5.5 V
Internal OSC, 6.5 MHz minute
6.5
MHz
2.785
t(conv)
Conversion time
Conversion clock is external source,
SCLK = 25 MHz (see Note 1)
2.895
μ
s
Acquisition time
Normal short sampling
1.2
μ
s
Throughput rate (see Note 2)
Normal long sampling, fixed channel in mode
00 or 01
200
KSPS
DC Accuracy
Normal Long Sampling
EL
ED
EO
E(g+)
All typical values are at TA = 25
°
C.
NOTES:
1. Conversion time t(conv) = (18x4 / SCLK) + 15 ns.
2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC (refer to Figure 8).
3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.
4. Zero offset error is the difference between 0000000000000 and the converted output for zero input voltage; gain error is the
difference between 11111111111111 and the converted output for full-scale input voltage. The full-scale input voltage is equal to the
reference voltage being used.
Integral linearity error
See Note 3
1
±
0.5
±
0.5
±
0.6
1
LSB
Differential linearity error
1
1
LSB
Zero offset error
See Note 4
3
3
LSB
Gain error
See Note 4
0
5
12
LSB
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