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iv
3.3.2 ADC Digital Filter, T
A
= 25
°
C, AV
DD
= DV
DD
= 3.3 V
±
10%,
f
s
= 44.1 kHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3
Analog-to-Digital Converter,
T
A
= 25
°
C, AV
DD
= DV
DD
= 3.3 V, f
s
= 44.1 kHz
3.3.4
DAC Interpolation Filter, T
A
= 25
°
C, AV
DD
= DV
DD
= 3.3 V + 10%,
f
s
= 44.1 kHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5
Digital-to-Analog Converter, T
A
= 25
°
C, AV
DD
= 3.3 V, f
s
= 44.1 kHz,
Input = 1 V
rms
Sine Wave at 1 kHz
3.3.6 Output Performance Data T
A
= 25
°
C, AV
DD
= DV
DD
= 3.3 V
±
10%
Serial Interface Switching Characteristics,
T
A
= 25
°
C, AV
DD
= DV
DD
= 3.3 V
±
10%
DSP Serial Interface Switching Characteristics,
T
A
= 25
°
C, AV
DD
= DV
DD
= 3.3 V
±
10%
Parameter Measurement Information
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Application Information
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5.1
Single-Ended to Differential External Analog
Front-End Circuit (f
s
= 44.1 kHz)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
External Analog Back-End Circuit (f
s
= 44.1 kHz)
Appendix A Mechanical Data
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3–2
3–2
. . . . . . . . . . . . . . . . . . . .
3–2
3–3
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . .
3.4
3–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
3–4
4–1
5–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
5–1
5–2
A–1
. . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations
Title
Figure
2–1 MSB First Right/Left Justified (for 16-, 20-, and 24-bits)
2–2 IIS-Compatible Serial Format (for 16-, 20-, and 24-bits)
2–3 MSB Left Justified Serial Interface Format (for 16-bits)
2–4 DSP Compatible Serial Interface Format (for 16-bits)
2–5 De-Emphasis Characteristics
4–1 Master Clock Timing
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4–2 Right/Left Justified, IIS, Left/Left Justified Serial Protocol Timing
4–3 DSP Serial Port Timing
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4–4 DAC Filter Overall Frequency Characteristics
4–5 DAC Digital Filter Passband Ripple Characteristics
4–6 ADC Digital Filter Characteristics
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4–7 ADC Digital Filter Stopband Characteristics
4–8 ADC Digital Filter Passband Characteristics
4–9 ADC High Pass Filter Characteristics
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5–1 Analog Front End (right channel) for 0.7 Vrms Input
5–2 Analog Back End (right channel) for 0.7 Vrms Output
5–3 Voltage Reference Connections
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Page
2–3
2–4
2–4
2–5
2–6
4–1
4–1
4–1
4–2
4–2
4–2
4–3
4–3
4–3
5–1
5–2
5–3
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List of Tables
Title
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table
2–1 Example Master Clock Frequency Rates
Page
2–5