參數(shù)資料
型號: TLC320AD58C
廠商: Texas Instruments, Inc.
英文描述: Sigma-Delta Stereo Analog-to-Digital Converter
中文描述: Σ-Δ立體聲模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 14/27頁
文件大小: 178K
代理商: TLC320AD58C
2–6
Several modes are available when the TLC320AD58C is configured as a slave. Using the Mode0, Mode1,
and Mode2 terminals, the TLC320AD58C can be set to shift out the MSB first or the LSB first [see Figures
2–4(a) and 2–4(b)]. The number of bits shifted out, however, can be controlled by the number of valid SCLK
cycles provided within the left or right channel period. If only enough clocks are provided to shift out 16 data
bits before LRClk changes state, then this is equivalent to a 16-bit mode. Modes 1 and 2 both require 64
SCLK periods per LRClk period.
. . .
17
16
. . .
1
0
17
16
. . .
1
0
32–128 SCLKs
SCLK
Fsync
DOUT
input
LRClk
Mode 000
(a) 18-BIT SLAVE MODE (Fsync high)
(b) 18-BIT SLAVE MODE (Fsync high)
SCLK
Fsync
DOUT
LRClk
Mode 001
input
output
input
0
1
. . .
16
17
0
1
. . .
16
17
64 SCLKs
17
. . .
0
17
. . .
0
17
. . .
0
17
0
32–128 SCLKs
(c) 18-BIT SLAVE MODE (Fsync controlled)
SCLK
Fsync_1
DOUT_1
Mode 010
LRClk
Fsync_2
DOUT_2
Left
Right
Left
Right
Left
Right
Figure 2–4. Serial Slave Transfer Modes
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