參數(shù)資料
型號: TLC320AD535C-I
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: DUAL CHANNEL VOICE/DATA CODEC
中文描述: 雙通道語音/數(shù)據(jù)編解碼器
文件頁數(shù): 36/84頁
文件大?。?/td> 447K
代理商: TLC320AD535C-I
2–21
The default value of the A-register data is decimal 18 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
1
0
1
0
0
0
2.20.3
The following command loads DS07 (MSB) – DS00 into the B register.
Register 2 (B Register)
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
R/W
0
1
0
0
0
Register Data
Control Bits
The data in DS07 – DS00 controls the division of FCLK to generate the conversion clock as given in
equation 20:
Conversion frequency
FCLK (B register contents)
MCLK
2
A register contents
B register contents
(20)
The default value of the B-register data is decimal 18 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
1
0
1
0
0
0
2.20.4
The following command contains the A
-register address and loads DS07(MSB) – DS00 into the A
register.
Register 3 (A
Register)
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
R/W
0
1
0
1
0
Register Data
Control Bits
The data in DS07 – DS00 is in 2s-complement format and controls the number of master-clock periods that
the sampling time is shifted.
The default value of the A
-register data is 0 as shown below.
DS07
DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
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相關代理商/技術參數(shù)
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