- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69493 > TLC320AD50IPTR (TEXAS INSTRUMENTS INC) SPECIALTY ANALOG CIRCUIT, PQFP48 PDF資料下載
參數(shù)資料
| 型號： | TLC320AD50IPTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, QFP-48 |
| 文件頁數(shù)： | 15/52頁 |
| 文件大小： | 276K |
| 代理商： | TLC320AD50IPTR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
2–7
2.2.2.2 Hardware Power Down
When PWRDWN is held low, the device enters the hardware power-down mode. In this state, the internal clock control
circuit and the differential outputs OUTP and OUTM are disabled. All other digital I/Os either are disabled or remain
in the state they were in immediately before power down. DIN cannot accept any data input. The device can only be
returned to normal operation by taking and holding PWRDWN high. When not holding the device in the hardware
power-down mode, PWRDWN should be tied high.
2.3
Master Clock Circuit
MCLK is the external master clock input. The internal clock circuit generates and distributes necessary clocks
throughout the device. An internal PLL circuit is used for upsampling to provide the appropriate clocks for the digital
filters and modulators.
When the device is in the master mode, SCLK and FS are derived from MCLK in order to provide clocking of the serial
communications between the device and its controller. When in the slave mode, SCLK and FS are both inputs.
2.4
Data Out (DOUT)
DOUT is placed in the high-impedance state on the rising edge of the frame sync. In the primary communication, the
data word is the ADC conversion result. In the secondary communication, the data is the register-read results when
requested by the read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are
all zeroes. The state of the master/slave (M/S) terminal is reflected by the MSB in secondary communication (DOUT,
bit DS15) and the LSB in the primary communication (DOUT, bit D0) while in 15 + 1 mode. When the device is in the
slave mode, DOUT remains in a high-impedance state until a nonzero value is written as a number of slaves in control
register 3 (bits D7 and D6).
2.4.1
Data Out, Master Mode
In the master mode, DOUT is taken from the high-impedance state by the falling edge of the frame sync (FS) that
is assigned to DOUT. The most significant data bit then appears first on DOUT.
2.4.2
Data Out, Slave Mode
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the input frame sync (FS).
The most significant data bit then appears on DOUT. When in the slave mode, DOUT is not enabled until the control
3 register is programmed with the number of slaves. This must be done even if there is only one slave device.
2.5
Data In (DIN)
In a primary communication, the data word is the input digital signal to the DAC channel. If the (15+1)-bit data format
is used, the LSB (D0) is used to request a secondary communication. In a secondary communication, the data is the
control and configuration data that sets the device for a particular function (see Section 3, Secondary Serial
Communication for details).
2.6
FC (Hardware Secondary Communication Request)
The FC input provides for hardware requests for secondary communications. FC works in conjunction with the LSB
of the primary data word. The signal on FC is latched on the rising edge of the primary frame sync (FS). FC should
be tied low if not used.
2.7
Frame-Sync Function for TLC320AD50C
The frame-sync signal (FS) indicates the device is ready to send and receive data. The data transfer out of DOUT
and into DIN begins on the falling edge of the frame-sync signal.
相關PDF資料 |
PDF描述 |
|---|---|
| TLC320AD50IPT | SPECIALTY ANALOG CIRCUIT, PQFP48 |
| TLC555QDRQ1 | PULSE; RECTANGULAR, 1.2 MHz, TIMER, PDSO8 |
| TLC7701MPWREPG4 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| TLC7705QPWREP | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| TLC7701MPWREP | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD52CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD52CPT | 功能描述:IC ANALOG INTERFACE W/MS 48-LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調變:是 S/N 比，標準 ADC / DAC (db):- 動態(tài)范圍，標準 ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應商設備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2 |
| TLC320AD535 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C-I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
發(fā)布緊急采購，3分鐘左右您將得到回復。